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[I] Open Synthesis suite

[T] Yosys is a framework for Verilog RTL synthesis. It currently has
[T] extensive Verilog-2005 support and provides a basic set of synthesis
[T] algorithms for various application domains

[U] http://www.clairexen.net/yosys/

[A] Claire Xenia Wolf <claire@clairexen.net>
[M] Rene Rebe <rene@t2-project.org>

[C] extra/development

[L] ISC
[S] Beta
[V] 0.39
[P] X -----5---9 500.000

[D] 827cb8c58e8f43649f808101d7f606a0699980158cba71b66e161329 yosys-0.39.tar.gz https://github.com/YosysHQ/yosys/archive/refs/tags/
[D] c5058f174f353dbd6c6e2a01edfb349f05ca7cc800ace0606df6038a yosys-abc-0cd90d0.tar.gz !https://github.com/YosysHQ/abc/archive/0cd90d0.tar.gz