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[I] Documenting the Lattice ECP5 bit-stream format

[T] Project Trellis enables a fully open-source flow for ECP5 FPGAs using
[T] Yosys for Verilog synthesis and nextpnr for place and route. Project
[T] Trellis itself provides the device database and tools for bitstream
[T] creation.

[U] https://github.com/SymbiFlow/prjtrellis

[A] The Project Trellis Authors
[M] Rene Rebe <rene@t2-project.org>

[C] extra/development

[L] MIT
[S] Beta
[V] 35f5aff
[P] X -----5---9 126.800

#[D] bdaff9e77e758afdc613771a89db70d7aeebdec00d6de466436d1812 prjtrellis-1.2.1.tar.gz https://github.com/YosysHQ/prjtrellis/archive/1.2.1/
[D] 76a08e1395cd2a51d5b41a2ca5187383c8b50b92fb033791a859b87a prjtrellis-35f5aff.tar.gz !https://codeload.github.com/SymbiFlow/prjtrellis/tar.gz/35f5aff
[D] c0dded48bd0e867e5c09f3fc5d503992e61e45fb3cc053fdfb606362 prjtrellis-db-35d900a.tar.gz !https://codeload.github.com/SymbiFlow/prjtrellis-db/tar.gz/35d900a