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[COPY] t2/package/*/iverilog/iverilog.desc
[COPY] Copyright (C) 2007 - 2026 The T2 SDE Project
[COPY] SPDX-License-Identifier: GPL-2.0
[COPY] --- T2-COPYRIGHT-END ---

[I] A Verilog simulation and synthesis tool

[T] Icarus Verilog is a Verilog simulation and synthesis tool. It operates
[T] as a compiler, compiling source code writen in Verilog (IEEE-1364) into
[T] some target format.

[U] http://iverilog.icarus.com/

[A] David Evans yevans@virginia.edu>
[M] René Rebe <rene@exactco.de>

[C] extra/development
[F] CROSS

[L] GPL
[V] 13.0

[CV-TR] s/\./_/
[D] f23ae26d1f2601695869c7eb449b8fd291d10bf78999667fd42d708d iverilog-13_0.tar.gz https://download.sourceforge.net/iverilog/

var_append makeinstopt ' ' -j1