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[COPY] t2/package/*/iverilog/iverilog.desc
[COPY] Copyright (C) 2007 - 2025 The T2 SDE Project
[COPY] SPDX-License-Identifier: GPL-2.0
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[I] A Verilog simulation and synthesis tool

[T] Icarus Verilog is a Verilog simulation and synthesis tool. It operates
[T] as a compiler, compiling source code writen in Verilog (IEEE-1364) into
[T] some target format.

[U] http://iverilog.icarus.com/

[A] David Evans yevans@virginia.edu>
[M] T2 Project <t2@t2-project.org>

[C] extra/development
[F] CROSS

[L] GPL
[S] Beta
[V] 12.0

var_append makeinstopt ' ' -j1

[D] ac6f6e8008a00828dc3334a96f7f8c43f7dbe635f44f829d23d223b9 verilog-12.0.tar.gz http://dl.sourceforge.net/iverilog/