# --- T2-COPYRIGHT-NOTE-BEGIN --- # T2 SDE: package/*/xf86-video-sis/add-xgi-21-volari-z9.patch # Copyright (C) 2024 The T2 SDE Project # # This Copyright note is generated by scripts/Create-CopyPatch, # more information can be found in the files COPYING and README. # # This patch file is dual-licensed. It is available under the license the # patched project is licensed under, as long as it is an OpenSource license # as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms # of the GNU General Public License version 2 as used by the T2 SDE. # --- T2-COPYRIGHT-NOTE-END --- --- xf86-video-sis/src/sis_setup.c.vanilla 2024-04-04 13:14:41.131562002 +0000 +++ xf86-video-sis/src/sis_setup.c 2024-04-04 13:22:35.416579598 +0000 @@ -551,6 +551,7 @@ case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: if(pSiS->ChipType != XGI_20) { /* SIS340, XGI_40 */ @@ -931,6 +932,7 @@ case PCI_CHIP_SIS330: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: sis315Setup(pScrn); break; --- xf86-video-sis/src/sis_driver.c.vanilla 2024-04-04 13:15:35.676564025 +0000 +++ xf86-video-sis/src/sis_driver.c 2024-04-04 13:32:21.369601337 +0000 @@ -213,12 +213,14 @@ static SymTabRec XGIChipsets[] = { { PCI_CHIP_XGIXG20, "Volari Z7 (XG20)" }, + { PCI_CHIP_XGIXG21, "Volari Z9 (XG21)" }, { PCI_CHIP_XGIXG40, "Volari V3XT/V5/V8/Duo (XG40)" }, { -1, NULL } }; static PciChipsets XGIPciChipsets[] = { { PCI_CHIP_XGIXG20, PCI_CHIP_XGIXG20, RES_SHARED_VGA }, + { PCI_CHIP_XGIXG21, PCI_CHIP_XGIXG21, RES_SHARED_VGA }, { PCI_CHIP_XGIXG40, PCI_CHIP_XGIXG40, RES_SHARED_VGA }, { -1, -1, RES_UNDEFINED } }; @@ -3426,6 +3428,7 @@ case PCI_CHIP_SIS660: /* 660, 661, 741, 760, 761, 670(?), 770 */ case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: pSiS->VGAEngine = SIS_315_VGA; break; @@ -3812,6 +3815,7 @@ pSiS->NewCRLayout = TRUE; break; case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: pSiS->ChipType = XGI_20; pSiS->ChipFlags |= (SiSCF_XabreCore | SiSCF_MMIOPalette | SiSCF_IsXGI); pSiS->SiS_SD2_Flags |= (SiS_SD2_NOOVERLAY | SiS_SD2_ISXGI); --- xf86-video-sis/src/sis.h.vanilla 2024-04-04 13:17:24.299568055 +0000 +++ xf86-video-sis/src/sis.h 2024-04-04 13:17:48.009568935 +0000 @@ -343,6 +343,7 @@ * XGI Technology PCI Device ID */ #define PCI_CHIP_XGIXG20 0x0020 +#define PCI_CHIP_XGIXG21 0x0021 #define PCI_CHIP_XGIXG40 0x0040 --- xf86-video-sis/src/sis310_accel.c.vanilla 2024-04-04 13:19:43.119573206 +0000 +++ xf86-video-sis/src/sis310_accel.c 2024-04-04 13:20:55.812575903 +0000 @@ -2038,6 +2038,7 @@ (pSiS->Chipset != PCI_CHIP_SIS330) && (pSiS->Chipset != PCI_CHIP_SIS340) && (pSiS->Chipset != PCI_CHIP_XGIXG20) && + (pSiS->Chipset != PCI_CHIP_XGIXG21) && (pSiS->Chipset != PCI_CHIP_XGIXG40)) { infoPtr->SubsequentSolidFillTrap = SiSSubsequentSolidFillTrap; } @@ -2065,6 +2066,7 @@ (pSiS->Chipset != PCI_CHIP_SIS330) && (pSiS->Chipset != PCI_CHIP_SIS340) && (pSiS->Chipset != PCI_CHIP_XGIXG20) && + (pSiS->Chipset != PCI_CHIP_XGIXG21) && (pSiS->Chipset != PCI_CHIP_XGIXG40)) { infoPtr->SubsequentMono8x8PatternFillTrap = SiSSubsequentMonoPatternFillTrap; } @@ -2139,6 +2141,7 @@ (pSiS->Chipset != PCI_CHIP_SIS330) && (pSiS->Chipset != PCI_CHIP_SIS340) && (pSiS->Chipset != PCI_CHIP_XGIXG20) && + (pSiS->Chipset != PCI_CHIP_XGIXG21) && (pSiS->Chipset != PCI_CHIP_XGIXG40)) { pSiS->ColorExpandBufferNumber = 16; pSiS->ColorExpandBufferCountMask = 0x0F; --- xf86-video-sis/src/sis_cursor.c.vanilla 2024-04-04 13:19:43.132573206 +0000 +++ xf86-video-sis/src/sis_cursor.c 2024-04-04 13:21:17.725576716 +0000 @@ -969,6 +969,7 @@ case PCI_CHIP_SIS660: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: if(mode->Flags & V_INTERLACE) return FALSE; @@ -1047,6 +1048,7 @@ case PCI_CHIP_SIS660: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: if(mode->Flags & V_INTERLACE) return FALSE; @@ -1402,6 +1404,7 @@ case PCI_CHIP_SIS660: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: infoPtr->MaxWidth = 64; infoPtr->MaxHeight = 64; --- xf86-video-sis/src/sis_dac.c.vanilla 2024-04-04 13:19:43.145573207 +0000 +++ xf86-video-sis/src/sis_dac.c 2024-04-04 13:21:48.033577840 +0000 @@ -1300,6 +1300,7 @@ case PCI_CHIP_SIS660: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: /* Numerator */ @@ -1492,6 +1493,7 @@ case PCI_CHIP_SIS660: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: switch(pSiS->Chipset) { case PCI_CHIP_SIS300: @@ -1532,6 +1534,7 @@ max = 800000; break; case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: magic = 1.0; /* magicDED[bus/64]; */ max = 332000; break; @@ -1975,6 +1978,7 @@ case PCI_CHIP_SIS660: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: pSiS->SiSSave = SiS315Save; pSiS->SiSRestore = SiS315Restore; --- xf86-video-sis/src/sis_vga.c.vanilla 2024-04-04 13:19:43.158573207 +0000 +++ xf86-video-sis/src/sis_vga.c 2024-04-04 13:22:53.451580267 +0000 @@ -1058,6 +1058,7 @@ case PCI_CHIP_SIS660: case PCI_CHIP_SIS340: case PCI_CHIP_XGIXG20: + case PCI_CHIP_XGIXG21: case PCI_CHIP_XGIXG40: pSiS->ModeInit = SIS300Init; break; --- xf86-video-sis/src/sis_video.c.vanilla 2024-04-04 13:19:43.172573208 +0000 +++ xf86-video-sis/src/sis_video.c 2024-04-04 13:23:38.913581954 +0000 @@ -486,6 +486,7 @@ } } else if((pSiS->Chipset == PCI_CHIP_SIS340) || (pSiS->Chipset == PCI_CHIP_XGIXG20) || + (pSiS->Chipset == PCI_CHIP_XGIXG21) || (pSiS->Chipset == PCI_CHIP_XGIXG40)) { /* Disable contrast enhancement (?) */ setvideoregmask(pSiS, Index_VI_Key_Overlay_OP, 0x00, 0x10); @@ -908,6 +909,7 @@ pPriv->is761 = (pSiS->ChipType == SIS_761) ? TRUE : FALSE; pPriv->is340 = (pSiS->Chipset == PCI_CHIP_SIS340) ? TRUE : FALSE; pPriv->isXGI = (pSiS->Chipset == PCI_CHIP_XGIXG20 || + pSiS->Chipset == PCI_CHIP_XGIXG21 || pSiS->Chipset == PCI_CHIP_XGIXG40) ? TRUE : FALSE; /* Setup chipset type helpers */ @@ -2288,6 +2290,7 @@ (pSiS->Chipset != PCI_CHIP_SIS660) && (pSiS->Chipset != PCI_CHIP_SIS340) && (pSiS->Chipset != PCI_CHIP_XGIXG20) && + (pSiS->Chipset != PCI_CHIP_XGIXG21) && (pSiS->Chipset != PCI_CHIP_XGIXG40)) { setvideoregmask(pSiS, Index_VI_Control_Misc2, mybool ? 0x04 : 0x00, 0x04); if(mybool) pOverlay->keyOP = VI_ROP_Always;