From: René Rebe <rene@exactco.de>
Subject: [PATCH] MIPS: IP32: use the CRIME irq chip for the RE level interrupts

The CRIME rendering engine level interrupts (FIFO empty, FIFO full and
idle, CRIME bits 25-27) fall into the default case of
arch_init_irq() and get the MACE ISA level irq chip. Masking and
unmasking them then changes MACE ISA bits instead of the CRIME interrupt
mask, so a rendering engine driver can never enable them. Treat them like
the other CRIME level interrupts.

Signed-off-by: René Rebe <rene@exactco.de>
---
--- a/arch/mips/sgi-ip32/ip32-irq.c	2026-10-22 10:26:06.414987468 +0200
+++ b/arch/mips/sgi-ip32/ip32-irq.c	2026-10-22 10:26:06.427316847 +0200
@@ -457,6 +457,7 @@ void __init arch_init_irq(void)
 
 		case CRIME_CPUERR_IRQ:
 		case CRIME_MEMERR_IRQ:
+		case CRIME_RE_EMPTY_L_IRQ ... CRIME_RE_IDLE_L_IRQ:
 			irq_set_chip_and_handler_name(irq,
 						      &crime_level_interrupt,
 						      handle_level_irq,