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[COPY] t2/package/*/yosys/yosys.desc
[COPY] Copyright (C) 2018 - 2025 The T2 SDE Project
[COPY] SPDX-License-Identifier: GPL-2.0
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[I] Open Synthesis suite

[T] Yosys is a framework for Verilog RTL synthesis. It currently has
[T] extensive Verilog-2005 support and provides a basic set of synthesis
[T] algorithms for various application domains

[U] https://yosyshq.net/yosys/

[A] Claire Xenia Wolf <claire@clairexen.net>
[M] Rene Rebe <rene@t2-project.org>

[C] extra/development

[L] ISC
[S] Beta
[V] 0.55

[D] 4ca438bccc4b64ddd64aee0eb6ec40e420d7b3d69fe479efcccb95ed yosys-0.55.tar.gz !https://github.com/YosysHQ/yosys/releases/download/v0.55/yosys.tar.gz

runpysetup=0 srcdir=.
var_append makeopt ' ' CONFIG=gcc
var_append makeinstopt ' ' CONFIG=gcc