[COPY] --- T2-COPYRIGHT-BEGIN --- [COPY] t2/package/*/yosys/yosys.desc [COPY] Copyright (C) 2018 - 2025 The T2 SDE Project [COPY] SPDX-License-Identifier: GPL-2.0 [COPY] --- T2-COPYRIGHT-END --- [I] Open Synthesis suite [T] Yosys is a framework for Verilog RTL synthesis. It currently has [T] extensive Verilog-2005 support and provides a basic set of synthesis [T] algorithms for various application domains [U] https://yosyshq.net/yosys/ [A] Claire Xenia Wolf [M] Rene Rebe [C] extra/development [L] ISC [S] Beta [V] 0.54 [D] cb0c9798d2c3aa4666e368d7faa689320c097e8e512524efc85523ff yosys-0.54.tar.gz !https://github.com/YosysHQ/yosys/releases/download/v0.54/yosys.tar.gz runpysetup=0 srcdir=. var_append makeopt ' ' CONFIG=gcc var_append makeinstopt ' ' CONFIG=gcc