[COPY] --- T2-COPYRIGHT-NOTE-BEGIN --- [COPY] T2 SDE: package/*/yosys/yosys.desc [COPY] Copyright (C) 2018 - 2023 The T2 SDE Project [COPY] [COPY] This Copyright note is generated by scripts/Create-CopyPatch, [COPY] more information can be found in the files COPYING and README. [COPY] [COPY] This program is free software; you can redistribute it and/or modify [COPY] it under the terms of the GNU General Public License version 2. [COPY] --- T2-COPYRIGHT-NOTE-END --- [I] Open Synthesis suite [T] Yosys is a framework for Verilog RTL synthesis. It currently has [T] extensive Verilog-2005 support and provides a basic set of synthesis [T] algorithms for various application domains [U] http://www.clairexen.net/yosys/ [A] Claire Xenia Wolf [M] Rene Rebe [C] extra/development [L] ISC [S] Beta [V] 0.29 [P] X -----5---9 126.800 [D] 4342338a841d95abc315b4ff2108e69cd7678eecf586db2a12aefc91 yosys-0.29.tar.gz https://github.com/YosysHQ/yosys/archive/refs/tags/ [D] 698f4c3e754213dc19e4560212ebcb115e3868512204a03ae8ef8f0f yosys-abc-2c1c83f.tar.gz !https://github.com/YosysHQ/abc/archive/2c1c83f.tar.gz