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[I] Open Synthesis suite

[T] Yosys is a framework for Verilog RTL synthesis. It currently has
[T] extensive Verilog-2005 support and provides a basic set of synthesis
[T] algorithms for various application domains

[U] http://www.clairexen.net/yosys/

[A] Claire Xenia Wolf <claire@clairexen.net>
[M] Rene Rebe <rene@t2-project.org>

[C] extra/development

[L] ISC
[S] Beta
[V] 0.29
[P] X -----5---9 126.800

[D] 4342338a841d95abc315b4ff2108e69cd7678eecf586db2a12aefc91 yosys-0.29.tar.gz https://github.com/YosysHQ/yosys/archive/refs/tags/
[D] 698f4c3e754213dc19e4560212ebcb115e3868512204a03ae8ef8f0f yosys-abc-2c1c83f.tar.gz !https://github.com/YosysHQ/abc/archive/2c1c83f.tar.gz