[COPY] --- T2-COPYRIGHT-BEGIN ---
[COPY] t2/package/*/yosys/yosys.desc
[COPY] Copyright (C) 2018 - 2026 The T2 SDE Project
[COPY] SPDX-License-Identifier: GPL-2.0
[COPY] --- T2-COPYRIGHT-END ---

[I] Open Synthesis suite

[T] Yosys is a framework for Verilog RTL synthesis. It currently has
[T] extensive Verilog-2005 support and provides a basic set of synthesis
[T] algorithms for various application domains

[U] https://yosyshq.net/yosys/

[A] Claire Xenia Wolf <claire@clairexen.net>
[M] Rene Rebe <rene@t2-project.org>

[C] extra/development

[L] ISC
[V] 0.63

[D] b337997fb640d37bf7694c69165b17addc721a0a1a603d0a9c697957 yosys-0.63.tar.gz !https://github.com/YosysHQ/yosys/releases/download/v0.63/yosys.tar.gz

runpysetup=0 srcdir=.
var_append makeopt ' ' CONFIG=gcc
var_append makeinstopt ' ' CONFIG=gcc