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[I] A Verilog simulation and synthesis tool

[T] Icarus Verilog is a Verilog simulation and synthesis tool. It operates
[T] as a compiler, compiling source code writen in Verilog (IEEE-1364) into
[T] some target format.

[U] http://iverilog.icarus.com/

[A] David Evans yevans@virginia.edu>
[M] T2 Project <t2@t2-project.org>

[C] extra/development
[F] CROSS

[L] GPL
[S] Beta
[V] 11.0
[P] X -----5---9 800.000

[O] var_append makeinstopt ' ' '-j1'

[D] 21f95132f2c3ff2652ed931193d29c974c6adfac5c96a9f7c3949f3d verilog-11.0.tar.gz http://dl.sourceforge.net/iverilog/