# --- T2-COPYRIGHT-BEGIN --- # t2/package/*/gdb/i860.patch.i860 # Copyright (C) 2026 The T2 SDE Project # SPDX-License-Identifier: GPL-2.0 or patched project license # --- T2-COPYRIGHT-END --- From: René Rebe Subject: [PATCH] i860: restore binutils support, add Linux, dynamic linking, TLS and gdb Restores the i860 port removed from binutils for current master: bfd, opcodes, gas and ld with i860-*-linux*, dynamic linking and TLS relocations, plus their test suites. Adds gdb/i860-tdep.c. Generated configure and Makefile.in were patched by hand and not regenerated. Against upstream commit 865dd73481041beb76bb5d47916451bd2a15036c ([gdb/testsuite] Fix copyright years in two files). Branch i860 at 16a662aeefc. Tested in the MAME magicst2 model only, not on real hardware. Signed-off-by: René Rebe Co-Authored-By: Claude Opus 5.5 --- bfd/Makefile.am | 5 + bfd/Makefile.in | 6 + bfd/archures.c | 4 + bfd/bfd-in2.h | 43 + bfd/config.bfd | 14 +- bfd/configure | 2 + bfd/configure.ac | 3 + bfd/cpu-i860.c | 44 + bfd/elf32-i860.c | 2601 +++++++++++++++++++ bfd/libbfd.h | 40 + bfd/po/SRC-POTFILES.in | 2 + bfd/reloc.c | 84 + bfd/targets.c | 5 + binutils/testsuite/binutils-all/objdump.exp | 2 +- gas/Makefile.am | 3 + gas/Makefile.in | 6 + gas/config/tc-i860.c | 1614 ++++++++++++ gas/config/tc-i860.h | 101 + gas/configure.tgt | 2 + gas/doc/all.texi | 1 + gas/doc/as.texi | 9 +- gas/doc/c-i860.texi | 197 ++ gas/doc/local.mk | 1 + gas/po/POTFILES.in | 2 + gas/testsuite/gas/all/gas.exp | 3 +- gas/testsuite/gas/i860/README.i860 | 39 + gas/testsuite/gas/i860/bitwise.d | 141 + gas/testsuite/gas/i860/bitwise.s | 150 ++ gas/testsuite/gas/i860/branch.d | 81 + gas/testsuite/gas/i860/branch.s | 85 + gas/testsuite/gas/i860/bte.d | 62 + gas/testsuite/gas/i860/bte.s | 55 + gas/testsuite/gas/i860/dir-align01.d | 17 + gas/testsuite/gas/i860/dir-align01.s | 11 + gas/testsuite/gas/i860/dir-intel01.d | 19 + gas/testsuite/gas/i860/dir-intel01.s | 19 + gas/testsuite/gas/i860/dir-intel02.d | 15 + gas/testsuite/gas/i860/dir-intel02.s | 13 + gas/testsuite/gas/i860/dir-intel03-err.l | 5 + gas/testsuite/gas/i860/dir-intel03-err.s | 14 + gas/testsuite/gas/i860/dual-frag.s | 10 + gas/testsuite/gas/i860/dual01.d | 21 + gas/testsuite/gas/i860/dual01.s | 17 + gas/testsuite/gas/i860/dual02-err.l | 2 + gas/testsuite/gas/i860/dual02-err.s | 9 + gas/testsuite/gas/i860/dual03.d | 53 + gas/testsuite/gas/i860/dual03.s | 46 + gas/testsuite/gas/i860/fldst01.d | 73 + gas/testsuite/gas/i860/fldst01.s | 75 + gas/testsuite/gas/i860/fldst02.d | 73 + gas/testsuite/gas/i860/fldst02.s | 75 + gas/testsuite/gas/i860/fldst03.d | 73 + gas/testsuite/gas/i860/fldst03.s | 75 + gas/testsuite/gas/i860/fldst04.d | 73 + gas/testsuite/gas/i860/fldst04.s | 75 + gas/testsuite/gas/i860/fldst05.d | 73 + gas/testsuite/gas/i860/fldst05.s | 75 + gas/testsuite/gas/i860/fldst06.d | 73 + gas/testsuite/gas/i860/fldst06.s | 75 + gas/testsuite/gas/i860/fldst07.d | 73 + gas/testsuite/gas/i860/fldst07.s | 75 + gas/testsuite/gas/i860/fldst08.d | 73 + gas/testsuite/gas/i860/fldst08.s | 75 + gas/testsuite/gas/i860/float01.d | 69 + gas/testsuite/gas/i860/float01.s | 84 + gas/testsuite/gas/i860/float02.d | 39 + gas/testsuite/gas/i860/float02.s | 42 + gas/testsuite/gas/i860/float03.d | 51 + gas/testsuite/gas/i860/float03.s | 64 + gas/testsuite/gas/i860/float04.d | 39 + gas/testsuite/gas/i860/float04.s | 49 + gas/testsuite/gas/i860/form.d | 63 + gas/testsuite/gas/i860/form.s | 66 + gas/testsuite/gas/i860/i860.exp | 63 + gas/testsuite/gas/i860/iarith.d | 97 + gas/testsuite/gas/i860/iarith.s | 102 + gas/testsuite/gas/i860/ldst01.d | 39 + gas/testsuite/gas/i860/ldst01.s | 35 + gas/testsuite/gas/i860/ldst02.d | 39 + gas/testsuite/gas/i860/ldst02.s | 35 + gas/testsuite/gas/i860/ldst03.d | 43 + gas/testsuite/gas/i860/ldst03.s | 39 + gas/testsuite/gas/i860/ldst04.d | 24 + gas/testsuite/gas/i860/ldst04.s | 19 + gas/testsuite/gas/i860/ldst05.d | 24 + gas/testsuite/gas/i860/ldst05.s | 19 + gas/testsuite/gas/i860/ldst06.d | 28 + gas/testsuite/gas/i860/ldst06.s | 22 + gas/testsuite/gas/i860/pfam.d | 153 ++ gas/testsuite/gas/i860/pfam.s | 182 ++ gas/testsuite/gas/i860/pfmam.d | 153 ++ gas/testsuite/gas/i860/pfmam.s | 182 ++ gas/testsuite/gas/i860/pfmsm.d | 153 ++ gas/testsuite/gas/i860/pfmsm.s | 182 ++ gas/testsuite/gas/i860/pfsm.d | 153 ++ gas/testsuite/gas/i860/pfsm.s | 182 ++ gas/testsuite/gas/i860/pic.d | 37 + gas/testsuite/gas/i860/pic.s | 23 + gas/testsuite/gas/i860/pseudo-ops01.d | 14 + gas/testsuite/gas/i860/pseudo-ops01.s | 10 + gas/testsuite/gas/i860/regress01.d | 21 + gas/testsuite/gas/i860/regress01.s | 19 + gas/testsuite/gas/i860/shift.d | 86 + gas/testsuite/gas/i860/shift.s | 90 + gas/testsuite/gas/i860/simd.d | 105 + gas/testsuite/gas/i860/simd.s | 119 + gas/testsuite/gas/i860/system.d | 72 + gas/testsuite/gas/i860/system.s | 76 + gas/testsuite/gas/i860/xp.d | 241 ++ gas/testsuite/gas/i860/xp.s | 266 ++ gdb/Makefile.in | 1 + gdb/configure.tgt | 5 + gdb/i860-tdep.c | 477 ++++ include/elf/i860.h | 11 + include/opcode/i860.h | 507 ++++ ld/Makefile.am | 2 + ld/Makefile.in | 2 + ld/configure.tgt | 6 + ld/emulparams/elf32_i860.sh | 24 + ld/po/BLD-POTFILES.in | 1 + ld/testsuite/ld-i860/ehframe-hdr.d | 9 + ld/testsuite/ld-i860/ehframe.s | 115 + ld/testsuite/ld-i860/ld-i860.exp | 32 + ld/testsuite/ld-i860/nonpic-shared.d | 4 + ld/testsuite/ld-i860/nonpic.s | 5 + ld/testsuite/ld-i860/shared-plt.d | 19 + ld/testsuite/ld-i860/shared-relocs.d | 14 + ld/testsuite/ld-i860/shared.s | 32 + ld/testsuite/ld-i860/static-got.d | 6 + ld/testsuite/ld-i860/static-got.s | 14 + ld/testsuite/ld-i860/tls-shared.d | 12 + ld/testsuite/ld-i860/tls-static.d | 11 + ld/testsuite/ld-i860/tls.s | 20 + opcodes/Makefile.am | 2 + opcodes/Makefile.in | 2 + opcodes/configure | 1 + opcodes/configure.ac | 2 + opcodes/disassemble.c | 7 + opcodes/disassemble.h | 2 + opcodes/i860-dis.c | 287 ++ opcodes/po/POTFILES.in | 1 + 141 files changed, 12204 insertions(+), 4 deletions(-) diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 110e78478d7..d9ab4d19845 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -1,6 +1,7 @@ ## Process this file with automake to generate Makefile.in # # Copyright (C) 2012-2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -117,6 +118,7 @@ ALL_MACHINES = \ cpu-h8300.lo \ cpu-hppa.lo \ cpu-i386.lo \ + cpu-i860.lo \ cpu-ia64.lo \ cpu-iamcu.lo \ cpu-ip2k.lo \ @@ -200,6 +202,7 @@ ALL_MACHINES_CFILES = \ cpu-h8300.c \ cpu-hppa.c \ cpu-i386.c \ + cpu-i860.c \ cpu-ia64.c \ cpu-iamcu.c \ cpu-ip2k.c \ @@ -315,6 +318,7 @@ BFD32_BACKENDS = \ elf32-h8300.lo \ elf32-hppa.lo \ elf32-i386.lo \ + elf32-i860.lo \ elf32-ip2k.lo \ elf32-iq2000.lo \ elf32-lm32.lo \ @@ -450,6 +454,7 @@ BFD32_BACKENDS_CFILES = \ elf32-h8300.c \ elf32-hppa.c \ elf32-i386.c \ + elf32-i860.c \ elf32-ip2k.c \ elf32-iq2000.c \ elf32-lm32.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index e41374fffc0..d6043f2a078 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -585,6 +585,7 @@ ALL_MACHINES = \ cpu-h8300.lo \ cpu-hppa.lo \ cpu-i386.lo \ + cpu-i860.lo \ cpu-ia64.lo \ cpu-iamcu.lo \ cpu-ip2k.lo \ @@ -668,6 +669,7 @@ ALL_MACHINES_CFILES = \ cpu-h8300.c \ cpu-hppa.c \ cpu-i386.c \ + cpu-i860.c \ cpu-ia64.c \ cpu-iamcu.c \ cpu-ip2k.c \ @@ -784,6 +786,7 @@ BFD32_BACKENDS = \ elf32-h8300.lo \ elf32-hppa.lo \ elf32-i386.lo \ + elf32-i860.lo \ elf32-ip2k.lo \ elf32-iq2000.lo \ elf32-lm32.lo \ @@ -919,6 +922,7 @@ BFD32_BACKENDS_CFILES = \ elf32-h8300.c \ elf32-hppa.c \ elf32-i386.c \ + elf32-i860.c \ elf32-ip2k.c \ elf32-iq2000.c \ elf32-lm32.c \ @@ -1495,6 +1499,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-h8300.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-hppa.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i386.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-i860.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-iamcu.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-ip2k.Plo@am__quote@ @@ -1590,6 +1595,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-h8300.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-hppa.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i386.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-i860.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ia64.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-ip2k.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-iq2000.Plo@am__quote@ diff --git a/bfd/archures.c b/bfd/archures.c index 18472b820bc..0218cc5b069 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -1,5 +1,6 @@ /* BFD library support routines for architectures. Copyright (C) 1990-2026 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe Hacked by John Gilmore and Steve Chamberlain of Cygnus Support. This file is part of BFD, the Binary File Descriptor library. @@ -197,6 +198,7 @@ DESCRIPTION .#define bfd_mach_mipsisa64r5 68 .#define bfd_mach_mipsisa64r6 69 .#define bfd_mach_mips_micromips 96 +. bfd_arch_i860, {* Intel 860. *} . bfd_arch_i386, {* Intel 386. *} .#define bfd_mach_i386_intel_syntax (1 << 0) .#define bfd_mach_i386_i8086 (1 << 1) @@ -665,6 +667,7 @@ extern const bfd_arch_info_type bfd_frv_arch; extern const bfd_arch_info_type bfd_h8300_arch; extern const bfd_arch_info_type bfd_hppa_arch; extern const bfd_arch_info_type bfd_i386_arch; +extern const bfd_arch_info_type bfd_i860_arch; extern const bfd_arch_info_type bfd_iamcu_arch; extern const bfd_arch_info_type bfd_ia64_arch; extern const bfd_arch_info_type bfd_ip2k_arch; @@ -753,6 +756,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_h8300_arch, &bfd_hppa_arch, &bfd_i386_arch, + &bfd_i860_arch, &bfd_iamcu_arch, &bfd_ia64_arch, &bfd_ip2k_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index abb0d30f2e3..60855c2fe43 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1454,6 +1454,7 @@ enum bfd_architecture #define bfd_mach_mipsisa64r5 68 #define bfd_mach_mipsisa64r6 69 #define bfd_mach_mips_micromips 96 + bfd_arch_i860, /* Intel 860. */ bfd_arch_i386, /* Intel 386. */ #define bfd_mach_i386_intel_syntax (1 << 0) #define bfd_mach_i386_i8086 (1 << 1) @@ -5929,6 +5930,48 @@ enum bfd_reloc_code_real BFD_RELOC_CRIS_DTPMOD, BFD_RELOC_CRIS_32_IE, + /* Intel i860 Relocations. */ + BFD_RELOC_860_COPY, + BFD_RELOC_860_GLOB_DAT, + BFD_RELOC_860_JUMP_SLOT, + BFD_RELOC_860_RELATIVE, + BFD_RELOC_860_PC26, + BFD_RELOC_860_PLT26, + BFD_RELOC_860_PC16, + BFD_RELOC_860_LOW0, + BFD_RELOC_860_SPLIT0, + BFD_RELOC_860_LOW1, + BFD_RELOC_860_SPLIT1, + BFD_RELOC_860_LOW2, + BFD_RELOC_860_SPLIT2, + BFD_RELOC_860_LOW3, + BFD_RELOC_860_LOGOT0, + BFD_RELOC_860_SPGOT0, + BFD_RELOC_860_LOGOT1, + BFD_RELOC_860_SPGOT1, + BFD_RELOC_860_LOGOTOFF0, + BFD_RELOC_860_SPGOTOFF0, + BFD_RELOC_860_LOGOTOFF1, + BFD_RELOC_860_SPGOTOFF1, + BFD_RELOC_860_LOGOTOFF2, + BFD_RELOC_860_LOGOTOFF3, + BFD_RELOC_860_LOPC, + BFD_RELOC_860_HIGHADJ, + BFD_RELOC_860_HAGOT, + BFD_RELOC_860_HAGOTOFF, + BFD_RELOC_860_HAPC, + BFD_RELOC_860_HIGH, + BFD_RELOC_860_HIGOT, + BFD_RELOC_860_HIGOTOFF, + BFD_RELOC_860_TLS_GD_HI, + BFD_RELOC_860_TLS_GD_LO, + BFD_RELOC_860_TLS_IE_HA, + BFD_RELOC_860_TLS_IE_LO1, + BFD_RELOC_860_TLS_IE_ABS_HA, + BFD_RELOC_860_TLS_IE_ABS_LO1, + BFD_RELOC_860_TLS_LE_HI, + BFD_RELOC_860_TLS_LE_LO, + /* OpenRISC 1000 Relocations. */ BFD_RELOC_OR1K_REL_26, BFD_RELOC_OR1K_SLO16, diff --git a/bfd/config.bfd b/bfd/config.bfd index 9900e5c7470..c55af052d8a 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -1,6 +1,7 @@ # config.bfd # # Copyright (C) 2012-2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -124,7 +125,6 @@ case $targ in i[3-7]86-none-* | \ i[3-7]86-*-aout* | i[3-7]86*-*-vsta* | \ i370-* | \ - i860-*-* | \ i960-*-* | \ m68*-*-bsd* | \ m68*-*-aout* | \ @@ -641,6 +641,18 @@ case "${targ}" in targ_selvecs="i386_msdos_vec i386_aout_vec" ;; + i860-*-linux*) + targ_defvec=i860_elf32_le_vec + targ_selvecs=i860_elf32_vec + ;; + i860-stardent-sysv4* | i860-stardent-elf*) + targ_defvec=i860_elf32_le_vec + targ_selvecs="i860_elf32_vec i860_elf32_le_vec" + ;; + i860-*-sysv4* | i860-*-elf*) + targ_defvec=i860_elf32_vec + ;; + #ifdef BFD64 ia64*-*-freebsd* | ia64*-*-netbsd* | ia64*-*-linux-* | ia64*-*-elf* | ia64*-*-kfreebsd*-gnu) targ_defvec=ia64_elf64_le_vec diff --git a/bfd/configure b/bfd/configure index d010a3f9aa6..ede8f6860cf 100755 --- a/bfd/configure +++ b/bfd/configure @@ -16143,6 +16143,8 @@ do i386_pe_vec) tb="$tb pe-i386.lo peigen.lo $coff" ;; i386_pe_big_vec) tb="$tb pe-i386.lo peigen.lo $coff" ;; i386_pei_vec) tb="$tb pei-i386.lo peigen.lo $coff" ;; + i860_elf32_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;; + i860_elf32_le_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;; iamcu_elf32_vec) tb="$tb elf32-i386.lo $elfxx_x86 elf32.lo $elf" ;; ia64_elf32_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;; ia64_elf32_hpux_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index 0630973a11d..c5ca948718f 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -1,6 +1,7 @@ dnl Process this file with autoconf to produce a configure script. dnl dnl Copyright (C) 2012-2026 Free Software Foundation, Inc. +dnl Copyright (C) 2026 René Rebe dnl dnl This file is free software; you can redistribute it and/or modify dnl it under the terms of the GNU General Public License as published by @@ -480,6 +481,8 @@ do i386_pe_vec) tb="$tb pe-i386.lo peigen.lo $coff" ;; i386_pe_big_vec) tb="$tb pe-i386.lo peigen.lo $coff" ;; i386_pei_vec) tb="$tb pei-i386.lo peigen.lo $coff" ;; + i860_elf32_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;; + i860_elf32_le_vec) tb="$tb elf32-i860.lo elf32.lo $elf" ;; iamcu_elf32_vec) tb="$tb elf32-i386.lo $elfxx_x86 elf32.lo $elf" ;; ia64_elf32_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;; ia64_elf32_hpux_be_vec) tb="$tb elf32-ia64.lo elfxx-ia64.lo elf32.lo $elf" ;; diff --git a/bfd/cpu-i860.c b/bfd/cpu-i860.c new file mode 100644 index 00000000000..05427f14dbc --- /dev/null +++ b/bfd/cpu-i860.c @@ -0,0 +1,44 @@ +/* BFD support for the Intel 860 architecture. + Copyright (C) 1992-2018 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe + Created mostly by substituting "860" for "386" in cpu-i386.c + Harry Dolan , October 1995 + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +const bfd_arch_info_type bfd_i860_arch = +{ + 32, /* 32 bits in a word */ + 32, /* 32 bits in an address */ + 8, /* 8 bits in a byte */ + bfd_arch_i860, + 0, /* only 1 machine */ + "i860", + "i860", + 3, + true, /* the one and only */ + bfd_default_compatible, + bfd_default_scan, + bfd_arch_default_fill, + 0, + 0 /* Maximum offset of a reloc from the start of an insn. */ +}; diff --git a/bfd/elf32-i860.c b/bfd/elf32-i860.c new file mode 100644 index 00000000000..98a390ed397 --- /dev/null +++ b/bfd/elf32-i860.c @@ -0,0 +1,2601 @@ +/* Intel i860 specific support for 32-bit ELF. + Copyright (C) 1993-2018 Free Software Foundation, Inc. + + Full i860 support contributed by Jason Eckhardt . + Copyright (C) 2026 René Rebe + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/i860.h" + +/* special_function for R_860_PC26 relocation. */ +static bfd_reloc_status_type +i860_howto_pc26_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, + asymbol *symbol, + void *data ATTRIBUTE_UNUSED, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_vma insn; + bfd_vma relocation; + bfd_byte *addr; + + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + /* Used elf32-mips.c as an example. */ + if (bfd_is_und_section (symbol->section) + && output_bfd == (bfd *) NULL) + return bfd_reloc_undefined; + + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + relocation += reloc_entry->addend; + + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + /* Adjust for PC-relative relocation. */ + relocation -= (input_section->output_section->vma + + input_section->output_offset + + reloc_entry->address + + 4); + + /* Check for target out of range. */ + if ((bfd_signed_vma)relocation > (0x3ffffff << 2) + || (bfd_signed_vma)relocation < (-0x4000000 * 4)) + return bfd_reloc_outofrange; + + addr = (bfd_byte *) data + reloc_entry->address; + insn = bfd_get_32 (abfd, addr); + + relocation >>= reloc_entry->howto->rightshift; + insn = (insn & ~reloc_entry->howto->dst_mask) + | (relocation & reloc_entry->howto->dst_mask); + + bfd_put_32 (abfd, (bfd_vma) insn, addr); + + return bfd_reloc_ok; +} + +/* special_function for R_860_PC16 relocation. */ +static bfd_reloc_status_type +i860_howto_pc16_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void *data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_vma insn; + bfd_vma relocation; + bfd_byte *addr; + + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + /* Used elf32-mips.c as an example. */ + if (bfd_is_und_section (symbol->section) + && output_bfd == (bfd *) NULL) + return bfd_reloc_undefined; + + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + relocation += reloc_entry->addend; + + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + /* Adjust for PC-relative relocation. */ + relocation -= (input_section->output_section->vma + + input_section->output_offset + + reloc_entry->address + + 4); + + /* Check for target out of range. */ + if ((bfd_signed_vma)relocation > (0x7fff << 2) + || (bfd_signed_vma)relocation < (-0x8000 * 4)) + return bfd_reloc_outofrange; + + addr = (bfd_byte *) data + reloc_entry->address; + insn = bfd_get_32 (abfd, addr); + + relocation >>= reloc_entry->howto->rightshift; + relocation = (((relocation & 0xf800) << 5) | (relocation & 0x7ff)) + & reloc_entry->howto->dst_mask; + insn = (insn & ~reloc_entry->howto->dst_mask) | relocation; + + bfd_put_32 (abfd, (bfd_vma) insn, addr); + + return bfd_reloc_ok; +} + +/* special_function for R_860_HIGHADJ relocation. */ +static bfd_reloc_status_type +i860_howto_highadj_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void *data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_vma insn; + bfd_vma relocation; + bfd_byte *addr; + + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + /* Used elf32-mips.c as an example. */ + if (bfd_is_und_section (symbol->section) + && output_bfd == (bfd *) NULL) + return bfd_reloc_undefined; + + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + relocation += reloc_entry->addend; + relocation += 0x8000; + + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + addr = (bfd_byte *) data + reloc_entry->address; + insn = bfd_get_32 (abfd, addr); + + relocation = ((relocation >> 16) & 0xffff); + + insn = (insn & 0xffff0000) | relocation; + + bfd_put_32 (abfd, (bfd_vma) insn, addr); + + return bfd_reloc_ok; +} + +/* special_function for R_860_SPLITn relocations. */ +static bfd_reloc_status_type +i860_howto_splitn_reloc (bfd *abfd, + arelent *reloc_entry, + asymbol *symbol, + void *data, + asection *input_section, + bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_vma insn; + bfd_vma relocation; + bfd_byte *addr; + + if (output_bfd != NULL + && (symbol->flags & BSF_SECTION_SYM) == 0 + && (! reloc_entry->howto->partial_inplace + || reloc_entry->addend == 0)) + { + reloc_entry->address += input_section->output_offset; + return bfd_reloc_ok; + } + + /* Used elf32-mips.c as an example. */ + if (bfd_is_und_section (symbol->section) + && output_bfd == (bfd *) NULL) + return bfd_reloc_undefined; + + if (bfd_is_com_section (symbol->section)) + relocation = 0; + else + relocation = symbol->value; + + relocation += symbol->section->output_section->vma; + relocation += symbol->section->output_offset; + relocation += reloc_entry->addend; + + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + addr = (bfd_byte *) data + reloc_entry->address; + insn = bfd_get_32 (abfd, addr); + + relocation = (((relocation & 0xf800) << 5) | (relocation & 0x7ff)) + & reloc_entry->howto->dst_mask; + insn = (insn & ~reloc_entry->howto->dst_mask) | relocation; + + bfd_put_32 (abfd, (bfd_vma) insn, addr); + + return bfd_reloc_ok; +} + +/* This howto table is preliminary. */ +static reloc_howto_type elf32_i860_howto_table [] = +{ + /* This relocation does nothing. */ + HOWTO (R_860_NONE, /* type */ + 0, /* rightshift */ + 3, /* size (0 = byte, 1 = short, 2 = long) */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_NONE", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 32-bit absolute relocation. */ + HOWTO (R_860_32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_COPY, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_COPY", /* name */ + true, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_GLOB_DAT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_GLOB_DAT", /* name */ + true, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_JUMP_SLOT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_JUMP_SLOT", /* name */ + true, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_RELATIVE, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_RELATIVE", /* name */ + true, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 26-bit PC-relative relocation. */ + HOWTO (R_860_PC26, /* type */ + 2, /* rightshift */ + 4, /* size */ + 26, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + i860_howto_pc26_reloc, /* special_function */ + "R_860_PC26", /* name */ + false, /* partial_inplace */ + 0x3ffffff, /* src_mask */ + 0x3ffffff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_860_PLT26, /* type */ + 2, /* rightshift */ + 4, /* size */ + 26, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_PLT26", /* name */ + false, /* partial_inplace */ + 0x3ffffff, /* src_mask */ + 0x3ffffff, /* dst_mask */ + true), /* pcrel_offset */ + + /* A 16-bit PC-relative relocation. */ + HOWTO (R_860_PC16, /* type */ + 2, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + i860_howto_pc16_reloc, /* special_function */ + "R_860_PC16", /* name */ + false, /* partial_inplace */ + 0x1f07ff, /* src_mask */ + 0x1f07ff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_860_LOW0, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOW0", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_SPLIT0, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + i860_howto_splitn_reloc, /* special_function */ + "R_860_SPLIT0", /* name */ + false, /* partial_inplace */ + 0x1f07ff, /* src_mask */ + 0x1f07ff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOW1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOW1", /* name */ + false, /* partial_inplace */ + 0xfffe, /* src_mask */ + 0xfffe, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_SPLIT1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + i860_howto_splitn_reloc, /* special_function */ + "R_860_SPLIT1", /* name */ + false, /* partial_inplace */ + 0x1f07fe, /* src_mask */ + 0x1f07fe, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOW2, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOW2", /* name */ + false, /* partial_inplace */ + 0xfffc, /* src_mask */ + 0xfffc, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_SPLIT2, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + i860_howto_splitn_reloc, /* special_function */ + "R_860_SPLIT2", /* name */ + false, /* partial_inplace */ + 0x1f07fc, /* src_mask */ + 0x1f07fc, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOW3, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOW3", /* name */ + false, /* partial_inplace */ + 0xfff8, /* src_mask */ + 0xfff8, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOGOT0, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOGOT0", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_SPGOT0, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_SPGOT0", /* name */ + false, /* partial_inplace */ + 0x1f07ff, /* src_mask */ + 0x1f07ff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOGOT1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOGOT1", /* name */ + false, /* partial_inplace */ + 0xfffe, /* src_mask */ + 0xfffe, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_SPGOT1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_SPGOT1", /* name */ + false, /* partial_inplace */ + 0x1f07fe, /* src_mask */ + 0x1f07fe, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOGOTOFF0, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOGOTOFF0", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_SPGOTOFF0, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_SPGOTOFF0", /* name */ + false, /* partial_inplace */ + 0x1f07ff, /* src_mask */ + 0x1f07ff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOGOTOFF1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOGOTOFF1", /* name */ + false, /* partial_inplace */ + 0xfffe, /* src_mask */ + 0xfffe, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_SPGOTOFF1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_SPGOTOFF1", /* name */ + false, /* partial_inplace */ + 0x1f07fe, /* src_mask */ + 0x1f07fe, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOGOTOFF2, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOGOTOFF2", /* name */ + false, /* partial_inplace */ + 0xfffc, /* src_mask */ + 0xfffc, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOGOTOFF3, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOGOTOFF3", /* name */ + false, /* partial_inplace */ + 0xfff8, /* src_mask */ + 0xfff8, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_LOPC, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_LOPC", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_HIGHADJ, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + i860_howto_highadj_reloc, /* special_function */ + "R_860_HIGHADJ", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_HAGOT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_HAGOT", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_HAGOTOFF, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_HAGOTOFF", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_HAPC, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_HAPC", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_HIGH, /* type */ + 16, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_HIGH", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_HIGOT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_HIGOT", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_HIGOTOFF, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_HIGOTOFF", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_860_TLS_DTPMOD32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_DTPMOD32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_DTPOFF32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_DTPOFF32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_TPOFF32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_TPOFF32", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_GD_HI, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_GD_HI", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_GD_LO, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_GD_LO", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_IE_HA, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_IE_HA", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_IE_LO1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_IE_LO1", /* name */ + false, /* partial_inplace */ + 0xfffe, /* src_mask */ + 0xfffe, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_IE_ABS_HA, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_IE_ABS_HA", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_IE_ABS_LO1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_IE_ABS_LO1", /* name */ + false, /* partial_inplace */ + 0xfffe, /* src_mask */ + 0xfffe, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_LE_HI, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_LE_HI", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + HOWTO (R_860_TLS_LE_LO, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_860_TLS_LE_LO", /* name */ + false, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */}; + +static unsigned char elf_code_to_howto_index[R_860_max + 1]; + +static reloc_howto_type * +lookup_howto (unsigned int rtype) +{ + static int initialized = 0; + int i; + int howto_tbl_size = (int) (sizeof (elf32_i860_howto_table) + / sizeof (elf32_i860_howto_table[0])); + + if (! initialized) + { + initialized = 1; + memset (elf_code_to_howto_index, 0xff, + sizeof (elf_code_to_howto_index)); + for (i = 0; i < howto_tbl_size; i++) + elf_code_to_howto_index[elf32_i860_howto_table[i].type] = i; + } + + if (rtype >= R_860_max) + return NULL; + i = elf_code_to_howto_index[rtype]; + if (i >= howto_tbl_size) + return 0; + return elf32_i860_howto_table + i; +} + +/* Given a BFD reloc, return the matching HOWTO structure. */ +static reloc_howto_type * +elf32_i860_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int rtype; + + switch (code) + { + case BFD_RELOC_NONE: + rtype = R_860_NONE; + break; + case BFD_RELOC_32: + rtype = R_860_32; + break; + case BFD_RELOC_860_COPY: + rtype = R_860_COPY; + break; + case BFD_RELOC_860_GLOB_DAT: + rtype = R_860_GLOB_DAT; + break; + case BFD_RELOC_860_JUMP_SLOT: + rtype = R_860_JUMP_SLOT; + break; + case BFD_RELOC_860_RELATIVE: + rtype = R_860_RELATIVE; + break; + case BFD_RELOC_860_PC26: + rtype = R_860_PC26; + break; + case BFD_RELOC_860_PLT26: + rtype = R_860_PLT26; + break; + case BFD_RELOC_860_PC16: + rtype = R_860_PC16; + break; + case BFD_RELOC_860_LOW0: + rtype = R_860_LOW0; + break; + case BFD_RELOC_860_SPLIT0: + rtype = R_860_SPLIT0; + break; + case BFD_RELOC_860_LOW1: + rtype = R_860_LOW1; + break; + case BFD_RELOC_860_SPLIT1: + rtype = R_860_SPLIT1; + break; + case BFD_RELOC_860_LOW2: + rtype = R_860_LOW2; + break; + case BFD_RELOC_860_SPLIT2: + rtype = R_860_SPLIT2; + break; + case BFD_RELOC_860_LOW3: + rtype = R_860_LOW3; + break; + case BFD_RELOC_860_LOGOT0: + rtype = R_860_LOGOT0; + break; + case BFD_RELOC_860_SPGOT0: + rtype = R_860_SPGOT0; + break; + case BFD_RELOC_860_LOGOT1: + rtype = R_860_LOGOT1; + break; + case BFD_RELOC_860_SPGOT1: + rtype = R_860_SPGOT1; + break; + case BFD_RELOC_860_LOGOTOFF0: + rtype = R_860_LOGOTOFF0; + break; + case BFD_RELOC_860_SPGOTOFF0: + rtype = R_860_SPGOTOFF0; + break; + case BFD_RELOC_860_LOGOTOFF1: + rtype = R_860_LOGOTOFF1; + break; + case BFD_RELOC_860_SPGOTOFF1: + rtype = R_860_SPGOTOFF1; + break; + case BFD_RELOC_860_LOGOTOFF2: + rtype = R_860_LOGOTOFF2; + break; + case BFD_RELOC_860_LOGOTOFF3: + rtype = R_860_LOGOTOFF3; + break; + case BFD_RELOC_860_LOPC: + rtype = R_860_LOPC; + break; + case BFD_RELOC_860_HIGHADJ: + rtype = R_860_HIGHADJ; + break; + case BFD_RELOC_860_HAGOT: + rtype = R_860_HAGOT; + break; + case BFD_RELOC_860_HAGOTOFF: + rtype = R_860_HAGOTOFF; + break; + case BFD_RELOC_860_HAPC: + rtype = R_860_HAPC; + break; + case BFD_RELOC_860_HIGH: + rtype = R_860_HIGH; + break; + case BFD_RELOC_860_HIGOT: + rtype = R_860_HIGOT; + break; + case BFD_RELOC_860_HIGOTOFF: + rtype = R_860_HIGOTOFF; + break; + case BFD_RELOC_860_TLS_GD_HI: + rtype = R_860_TLS_GD_HI; + break; + case BFD_RELOC_860_TLS_GD_LO: + rtype = R_860_TLS_GD_LO; + break; + case BFD_RELOC_860_TLS_IE_HA: + rtype = R_860_TLS_IE_HA; + break; + case BFD_RELOC_860_TLS_IE_LO1: + rtype = R_860_TLS_IE_LO1; + break; + case BFD_RELOC_860_TLS_IE_ABS_HA: + rtype = R_860_TLS_IE_ABS_HA; + break; + case BFD_RELOC_860_TLS_IE_ABS_LO1: + rtype = R_860_TLS_IE_ABS_LO1; + break; + case BFD_RELOC_860_TLS_LE_HI: + rtype = R_860_TLS_LE_HI; + break; + case BFD_RELOC_860_TLS_LE_LO: + rtype = R_860_TLS_LE_LO; + break; + default: + rtype = 0; + break; + } + return lookup_howto (rtype); +} + +static reloc_howto_type * +elf32_i860_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, + const char *r_name) +{ + unsigned int i; + + for (i = 0; + i < (sizeof (elf32_i860_howto_table) + / sizeof (elf32_i860_howto_table[0])); + i++) + if (elf32_i860_howto_table[i].name != NULL + && strcasecmp (elf32_i860_howto_table[i].name, r_name) == 0) + return &elf32_i860_howto_table[i]; + + return NULL; +} + +/* Given a ELF reloc, return the matching HOWTO structure. */ +static bool +elf32_i860_info_to_howto_rela (bfd *abfd, + arelent *bfd_reloc, + Elf_Internal_Rela *elf_reloc) +{ + unsigned int r_type = ELF32_R_TYPE (elf_reloc->r_info); + + bfd_reloc->howto = lookup_howto (r_type); + if (bfd_reloc->howto == NULL) + { + /* xgettext:c-format */ + _bfd_error_handler (_("%pB: unsupported relocation type %#x"), + abfd, r_type); + bfd_set_error (bfd_error_bad_value); + return false; + } + return true; +} + +/* Specialized relocation handler for R_860_SPLITn. These relocations + involves a 16-bit field that is split into two contiguous parts. */ +static bfd_reloc_status_type +elf32_i860_relocate_splitn (bfd *input_bfd, + Elf_Internal_Rela *rello, + bfd_byte *contents, + bfd_vma value) +{ + bfd_vma insn; + reloc_howto_type *howto; + howto = lookup_howto ((unsigned) ELF32_R_TYPE (rello->r_info)); + insn = bfd_get_32 (input_bfd, contents + rello->r_offset); + + /* Relocate. */ + value += rello->r_addend; + + /* Separate the fields and insert. */ + value = (((value & 0xf800) << 5) | (value & 0x7ff)) & howto->dst_mask; + insn = (insn & ~howto->dst_mask) | value; + + bfd_put_32 (input_bfd, insn, contents + rello->r_offset); + return bfd_reloc_ok; +} + +/* Specialized relocation handler for R_860_PC16. This relocation + involves a 16-bit, PC-relative field that is split into two contiguous + parts. */ +static bfd_reloc_status_type +elf32_i860_relocate_pc16 (bfd *input_bfd, + asection *input_section, + Elf_Internal_Rela *rello, + bfd_byte *contents, + bfd_vma value) +{ + bfd_vma insn; + reloc_howto_type *howto; + howto = lookup_howto ((unsigned) ELF32_R_TYPE (rello->r_info)); + insn = bfd_get_32 (input_bfd, contents + rello->r_offset); + + /* Adjust for PC-relative relocation. */ + value -= (input_section->output_section->vma + + input_section->output_offset); + value -= rello->r_offset; + + /* Relocate. */ + value += rello->r_addend; + + /* Adjust the value by 4, then separate the fields and insert. */ + value -= 4; + if (((value & 0xffffffff) ^ 0x80000000) - 0x80000000 + 0x20000 >= 0x40000) + return bfd_reloc_overflow; + value >>= howto->rightshift; + value = (((value & 0xf800) << 5) | (value & 0x7ff)) & howto->dst_mask; + insn = (insn & ~howto->dst_mask) | value; + + bfd_put_32 (input_bfd, insn, contents + rello->r_offset); + return bfd_reloc_ok; + +} + +/* Specialized relocation handler for R_860_PC26. This relocation + involves a 26-bit, PC-relative field which must be adjusted by 4. */ +static bfd_reloc_status_type +elf32_i860_relocate_pc26 (bfd *input_bfd, + asection *input_section, + Elf_Internal_Rela *rello, + bfd_byte *contents, + bfd_vma value) +{ + bfd_vma insn; + reloc_howto_type *howto; + howto = lookup_howto ((unsigned) ELF32_R_TYPE (rello->r_info)); + insn = bfd_get_32 (input_bfd, contents + rello->r_offset); + + /* Adjust for PC-relative relocation. */ + value -= (input_section->output_section->vma + + input_section->output_offset); + value -= rello->r_offset; + + /* Relocate. */ + value += rello->r_addend; + + /* Adjust value by 4 and insert the field. */ + value -= 4; + if (((value & 0xffffffff) ^ 0x80000000) - 0x80000000 + 0x8000000 >= 0x10000000) + return bfd_reloc_overflow; + value = (value >> howto->rightshift) & howto->dst_mask; + insn = (insn & ~howto->dst_mask) | value; + + bfd_put_32 (input_bfd, insn, contents + rello->r_offset); + return bfd_reloc_ok; + +} + +/* Specialized relocation handler for R_860_HIGHADJ. */ +static bfd_reloc_status_type +elf32_i860_relocate_highadj (bfd *input_bfd, + Elf_Internal_Rela *rel, + bfd_byte *contents, + bfd_vma value) +{ + bfd_vma insn; + + insn = bfd_get_32 (input_bfd, contents + rel->r_offset); + + value += rel->r_addend; + value += 0x8000; + value = ((value >> 16) & 0xffff); + + insn = (insn & 0xffff0000) | value; + + bfd_put_32 (input_bfd, insn, contents + rel->r_offset); + return bfd_reloc_ok; +} + +/* Perform a single relocation. By default we use the standard BFD + routines. However, we handle some specially. */ +static bfd_reloc_status_type +i860_final_link_relocate (reloc_howto_type *howto, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + Elf_Internal_Rela *rel, + bfd_vma relocation) +{ + return _bfd_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, relocation, + rel->r_addend); +} + +/* Dynamic linking. r15 holds the address of _GLOBAL_OFFSET_TABLE_ in PIC + code, but a PLT entry does not depend on it: it finds its slot PC relative + and uses r28 to keep the return address across the call reading the PC. + There is no lazy binding entry, the C library binds all slots at load. */ + +#define PLT_ENTRY_SIZE 32 +#define PLT_ENTRY_WORD0 0xa03c0000 /* mov %r1,%r28 */ +#define PLT_ENTRY_WORD1 0x6c000001 /* call .+8 */ +#define PLT_ENTRY_WORD2 0xa0000000 /* nop */ +#define PLT_ENTRY_WORD3 0xec1f0000 /* orh ha(slot-.),%r0,%r31 */ +#define PLT_ENTRY_WORD4 0x83ff0800 /* addu %r1,%r31,%r31 */ +#define PLT_ENTRY_WORD5 0x17ff0001 /* ld.l l(slot-.)(%r31),%r31 */ +#define PLT_ENTRY_WORD6 0x4000f800 /* bri %r31 */ +#define PLT_ENTRY_WORD7 0xa3810000 /* mov %r28,%r1 */ +#define PLT_PC_OFFSET 12 /* of the return address of the call */ + +#define GOT_HEADER_WORDS 3 +#define ELF_DYNAMIC_INTERPRETER "/lib/ld.so.1" + +struct elf_i860_link_hash_entry +{ + struct elf_link_hash_entry root; + + /* Referenced by an absolute address in an instruction: a run time + relocation cannot fix that. */ + unsigned int has_insn_ref : 1; + + /* TLS accesses to this symbol, and their GOT entries. */ + unsigned char tls_mask; + bfd_vma tls_gd_got, tls_ie_got; +}; + +#define I860_TLS_GD 1 +#define I860_TLS_IE 2 + +/* Thread local storage, variant II: the block ends at the thread pointer in r30. */ +#define I860_LOCAL_GD(n) (n) /* in the local GOT array, after N entries */ +#define I860_LOCAL_IE(n) (2 * (n)) + +/* Whether a GOT entry of H needs a dynamic relocation with its symbol. */ +static int +i860_tls_dynsym (struct bfd_link_info *info, struct elf_link_hash_entry *h) +{ + return (h != NULL && h->dynindx != -1 + && elf_hash_table (info)->dynamic_sections_created + && !SYMBOL_REFERENCES_LOCAL (info, h)); +} + +#define i860_hash_table(p) elf_hash_table (p) + +static struct bfd_hash_entry * +i860_link_hash_newfunc (struct bfd_hash_entry *entry, + struct bfd_hash_table *table, const char *string) +{ + struct elf_i860_link_hash_entry *ret + = (struct elf_i860_link_hash_entry *) entry; + + if (ret == NULL) + ret = bfd_hash_allocate (table, sizeof (struct elf_i860_link_hash_entry)); + if (ret == NULL) + return NULL; + + ret = ((struct elf_i860_link_hash_entry *) + _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret, table, + string)); + if (ret != NULL) + { + ret->has_insn_ref = 0; + ret->tls_mask = 0; + ret->tls_gd_got = ret->tls_ie_got = (bfd_vma) -1; + } + return (struct bfd_hash_entry *) ret; +} + +static struct bfd_link_hash_table * +i860_link_hash_table_create (bfd *abfd) +{ + struct elf_link_hash_table *ret = bfd_zmalloc (sizeof *ret); + + if (ret == NULL) + return NULL; + if (!_bfd_elf_link_hash_table_init (ret, abfd, i860_link_hash_newfunc, + sizeof (struct elf_i860_link_hash_entry))) + { + free (ret); + return NULL; + } + return &ret->root; +} + +static void +i860_copy_indirect_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *dir, + struct elf_link_hash_entry *ind) +{ + ((struct elf_i860_link_hash_entry *) dir)->has_insn_ref + |= ((struct elf_i860_link_hash_entry *) ind)->has_insn_ref; + + ((struct elf_i860_link_hash_entry *) dir)->tls_mask + |= ((struct elf_i860_link_hash_entry *) ind)->tls_mask; + + _bfd_elf_link_hash_copy_indirect (info, dir, ind); +} + +static bool +i860_create_got (bfd *abfd, struct elf_link_hash_table *htab, + struct bfd_link_info *info) +{ + if (htab->sgot != NULL) + return true; + if (htab->dynobj == NULL) + htab->dynobj = abfd; + return _bfd_elf_create_got_section (htab->dynobj, info); +} + +static bool +i860_check_relocs (bfd *abfd, struct bfd_link_info *info, asection *sec, + const Elf_Internal_Rela *relocs) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + const Elf_Internal_Rela *rel; + const Elf_Internal_Rela *rel_end; + struct elf_link_hash_table *htab = i860_hash_table (info); + asection *sreloc = NULL; + + if (bfd_link_relocatable (info) || (sec->flags & SEC_ALLOC) == 0) + return true; + + symtab_hdr = &elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + + rel_end = relocs + sec->reloc_count; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h = NULL; + unsigned long r_symndx = ELF32_R_SYM (rel->r_info); + unsigned int r_type = ELF32_R_TYPE (rel->r_info); + + if (r_symndx >= symtab_hdr->sh_info) + { + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + if (strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0 + && !i860_create_got (abfd, htab, info)) + return false; + } + + switch (r_type) + { + case R_860_PC26: + case R_860_PLT26: + if (h != NULL) + { + h->needs_plt = 1; + h->plt.refcount += 1; + } + break; + + case R_860_TLS_GD_HI: + case R_860_TLS_GD_LO: + case R_860_TLS_IE_HA: + case R_860_TLS_IE_LO1: + case R_860_TLS_IE_ABS_HA: + case R_860_TLS_IE_ABS_LO1: + { + int gd = r_type == R_860_TLS_GD_HI || r_type == R_860_TLS_GD_LO; + + if ((r_type == R_860_TLS_IE_ABS_HA || r_type == R_860_TLS_IE_ABS_LO1) + && bfd_link_pic (info)) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%pB: relocation %s can not be used in position independent " + "output; recompile with -fPIC"), + abfd, lookup_howto (r_type)->name); + bfd_set_error (bfd_error_bad_value); + return 0; + } + if (!i860_create_got (abfd, htab, info)) + return 0; + if (!gd) + info->flags |= DF_STATIC_TLS; + if (h != NULL) + ((struct elf_i860_link_hash_entry *) h)->tls_mask + |= gd ? I860_TLS_GD : I860_TLS_IE; + else + { + unsigned int n = symtab_hdr->sh_info; + bfd_signed_vma *refs = elf_local_got_refcounts (abfd); + + if (refs == NULL) + { + refs = bfd_zalloc (abfd, 3 * n * sizeof (bfd_signed_vma)); + if (refs == NULL) + return 0; + elf_local_got_refcounts (abfd) = refs; + } + refs[(gd ? I860_LOCAL_GD (n) : I860_LOCAL_IE (n)) + r_symndx] = 1; + } + } + break; + + case R_860_TLS_LE_HI: + case R_860_TLS_LE_LO: + if (bfd_link_dll (info)) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%pB: relocation %s can not be used when making a shared " + "object; recompile with -fPIC"), + abfd, lookup_howto (r_type)->name); + bfd_set_error (bfd_error_bad_value); + return 0; + } + break; + + case R_860_LOGOT0: + case R_860_SPGOT0: + case R_860_LOGOT1: + case R_860_SPGOT1: + case R_860_HAGOT: + case R_860_HIGOT: + if (!i860_create_got (abfd, htab, info)) + return false; + if (h != NULL) + h->got.refcount += 1; + else + { + bfd_signed_vma *refs = elf_local_got_refcounts (abfd); + + if (refs == NULL) + { + /* also for the TLS entries of local symbols */ + refs = bfd_zalloc (abfd, (3 * symtab_hdr->sh_info + * sizeof (bfd_signed_vma))); + if (refs == NULL) + return false; + elf_local_got_refcounts (abfd) = refs; + } + refs[r_symndx] += 1; + } + break; + + case R_860_LOGOTOFF0: + case R_860_SPGOTOFF0: + case R_860_LOGOTOFF1: + case R_860_SPGOTOFF1: + case R_860_LOGOTOFF2: + case R_860_LOGOTOFF3: + case R_860_HAGOTOFF: + case R_860_HIGOTOFF: + if (!i860_create_got (abfd, htab, info)) + return false; + break; + + case R_860_HIGH: + case R_860_HIGHADJ: + case R_860_LOW0: + case R_860_LOW1: + case R_860_LOW2: + case R_860_LOW3: + case R_860_SPLIT0: + case R_860_SPLIT1: + case R_860_SPLIT2: + if (bfd_link_pic (info)) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%pB: relocation %s against `%s' can not be used when " + "making a shared object; recompile with -fPIC"), + abfd, lookup_howto (r_type)->name, + h != NULL ? h->root.root.string : "a local symbol"); + bfd_set_error (bfd_error_bad_value); + return false; + } + if (h != NULL) + { + h->non_got_ref = 1; + h->plt.refcount += 1; + h->pointer_equality_needed = 1; + ((struct elf_i860_link_hash_entry *) h)->has_insn_ref = 1; + } + break; + + case R_860_32: + if (h != NULL && !bfd_link_pic (info)) + { + h->non_got_ref = 1; + h->plt.refcount += 1; + h->pointer_equality_needed = 1; + } + + /* A shared object must copy these relocs, an executable may need + them for symbols of a shared object if it avoids a copy reloc. */ + if (bfd_link_pic (info) + || (h != NULL + && (h->root.type == bfd_link_hash_defweak + || !h->def_regular))) + { + struct elf_dyn_relocs *p; + struct elf_dyn_relocs **head; + + if (sreloc == NULL) + { + if (htab->dynobj == NULL) + htab->dynobj = abfd; + sreloc = _bfd_elf_make_dynamic_reloc_section + (sec, htab->dynobj, 2, abfd, true); + if (sreloc == NULL) + return false; + } + + if (h != NULL) + head = &h->dyn_relocs; + else + { + Elf_Internal_Sym *isym; + asection *s; + void *vpp; + + isym = bfd_sym_from_r_symndx (&htab->sym_cache, abfd, r_symndx); + if (isym == NULL) + return false; + s = bfd_section_from_elf_index (abfd, isym->st_shndx); + if (s == NULL) + s = sec; + vpp = &elf_section_data (s)->local_dynrel; + head = (struct elf_dyn_relocs **) vpp; + } + + p = *head; + if (p == NULL || p->sec != sec) + { + p = bfd_alloc (htab->dynobj, sizeof *p); + if (p == NULL) + return false; + p->next = *head; + *head = p; + p->sec = sec; + p->count = 0; + p->pc_count = 0; + } + p->count += 1; + } + break; + + default: + break; + } + } + return true; +} + +static bool +i860_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) +{ + struct elf_link_hash_table *htab = i860_hash_table (info); + asection *s, *srel; + + if (h->type == STT_FUNC || h->needs_plt) + { + /* A call to a symbol no dynamic object knows needs no PLT entry. */ + if (!bfd_link_pic (info) + && !h->def_dynamic + && !h->ref_dynamic + && h->root.type != bfd_link_hash_undefweak + && h->root.type != bfd_link_hash_undefined) + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + return true; + } + h->plt.offset = (bfd_vma) -1; + + if (h->is_weakalias) + { + struct elf_link_hash_entry *def = weakdef (h); + + BFD_ASSERT (def->root.type == bfd_link_hash_defined); + h->root.u.def.section = def->root.u.def.section; + h->root.u.def.value = def->root.u.def.value; + return true; + } + + /* Shared objects reach data of other objects through the GOT only. */ + if (bfd_link_pic (info) || !h->non_got_ref) + return true; + + /* Keep plain dynamic relocs instead of a copy reloc where possible. */ + if (info->nocopyreloc + || (!((struct elf_i860_link_hash_entry *) h)->has_insn_ref + && !_bfd_elf_readonly_dynrelocs (h))) + { + h->non_got_ref = 0; + return true; + } + + if ((h->root.u.def.section->flags & SEC_READONLY) != 0) + { + s = htab->sdynrelro; + srel = htab->sreldynrelro; + } + else + { + s = htab->sdynbss; + srel = htab->srelbss; + } + if ((h->root.u.def.section->flags & SEC_ALLOC) != 0 && h->size != 0) + { + srel->size += sizeof (Elf32_External_Rela); + h->needs_copy = 1; + } + return _bfd_elf_adjust_dynamic_copy (info, h, s); +} + +static bool +i860_allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf) +{ + struct bfd_link_info *info = (struct bfd_link_info *) inf; + struct elf_link_hash_table *htab = i860_hash_table (info); + struct elf_dyn_relocs *p; + bool dyn = htab->dynamic_sections_created; + + if (h->root.type == bfd_link_hash_indirect) + return true; + + if (dyn && h->plt.refcount > 0) + { + if (h->dynindx == -1 && !h->forced_local + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h) + && !bfd_elf_link_record_dynamic_symbol (info, h)) + return false; + + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h) + && !SYMBOL_CALLS_LOCAL (info, h)) + { + asection *s = htab->splt; + + h->plt.offset = s->size; + + /* The address of a function of a shared object taken in the + executable is its PLT entry, for pointer equality. */ + if (!bfd_link_pic (info) && !h->def_regular) + { + h->root.u.def.section = s; + h->root.u.def.value = h->plt.offset; + } + + s->size += PLT_ENTRY_SIZE; + htab->sgotplt->size += 4; + htab->srelplt->size += sizeof (Elf32_External_Rela); + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + + if (((struct elf_i860_link_hash_entry *) h)->tls_mask) + { + struct elf_i860_link_hash_entry *th = (struct elf_i860_link_hash_entry *) h; + asection *sgot = elf_hash_table (info)->sgot; + asection *srelgot = elf_hash_table (info)->srelgot; + + if (h->dynindx == -1 && !h->forced_local + && elf_hash_table (info)->dynamic_sections_created + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h) + && !bfd_elf_link_record_dynamic_symbol (info, h)) + return 0; + + if (th->tls_mask & I860_TLS_GD) + { + th->tls_gd_got = sgot->size; + sgot->size += 8; + if (i860_tls_dynsym (info, h)) + srelgot->size += 2 * sizeof (Elf32_External_Rela); + else if (bfd_link_pic (info)) + srelgot->size += sizeof (Elf32_External_Rela); + } + if (th->tls_mask & I860_TLS_IE) + { + th->tls_ie_got = sgot->size; + sgot->size += 4; + if (i860_tls_dynsym (info, h) || bfd_link_pic (info)) + srelgot->size += sizeof (Elf32_External_Rela); + } + } + + if (h->got.refcount > 0) + { + if (h->dynindx == -1 && !h->forced_local + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h) + && !bfd_elf_link_record_dynamic_symbol (info, h)) + return false; + + h->got.offset = htab->sgot->size; + htab->sgot->size += 4; + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, bfd_link_pic (info), h)) + htab->srelgot->size += sizeof (Elf32_External_Rela); + } + else + h->got.offset = (bfd_vma) -1; + + if (h->dyn_relocs == NULL) + return true; + + if (bfd_link_pic (info)) + { + if (h->root.type == bfd_link_hash_undefweak) + { + /* A RELATIVE reloc would turn the zero into the load address. */ + if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + h->dyn_relocs = NULL; + else if (h->dynindx == -1 && !h->forced_local + && !bfd_elf_link_record_dynamic_symbol (info, h)) + return false; + } + } + else + { + /* Drop relocs of symbols that got a copy reloc or are not dynamic. */ + if (!h->non_got_ref + && ((h->def_dynamic && !h->def_regular) + || (dyn + && (h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined)))) + { + if (h->dynindx == -1 && !h->forced_local + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h) + && !bfd_elf_link_record_dynamic_symbol (info, h)) + return false; + if (h->dynindx == -1) + h->dyn_relocs = NULL; + } + else + h->dyn_relocs = NULL; + } + + for (p = h->dyn_relocs; p != NULL; p = p->next) + elf_section_data (p->sec)->sreloc->size + += p->count * sizeof (Elf32_External_Rela); + return true; +} + +static bool +i860_late_size_sections (struct bfd_link_info *info) +{ + struct elf_link_hash_table *htab = i860_hash_table (info); + bfd *dynobj = htab->dynobj; + bool relocs = false; + asection *s; + bfd *ibfd; + + if (dynobj == NULL) + return true; + + if (htab->dynamic_sections_created + && bfd_link_executable (info) && !info->nointerp) + { + s = htab->interp; + BFD_ASSERT (s != NULL); + s->size = sizeof ELF_DYNAMIC_INTERPRETER; + s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER; + s->alloced = 1; + } + + /* GOT entries and dynamic relocs of local symbols. */ + for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) + { + bfd_signed_vma *local_got, *end_local_got; + + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) + continue; + + for (s = ibfd->sections; s != NULL; s = s->next) + { + struct elf_dyn_relocs *p; + + for (p = ((struct elf_dyn_relocs *) + elf_section_data (s)->local_dynrel); + p != NULL; p = p->next) + if (!(!bfd_is_abs_section (p->sec) + && bfd_is_abs_section (p->sec->output_section)) + && p->count != 0) + { + elf_section_data (p->sec)->sreloc->size + += p->count * sizeof (Elf32_External_Rela); + if ((p->sec->output_section->flags & SEC_READONLY) != 0) + info->flags |= DF_TEXTREL; + } + } + + local_got = elf_local_got_refcounts (ibfd); + if (local_got == NULL) + continue; + + end_local_got = local_got + elf_tdata (ibfd)->symtab_hdr.sh_info; + for (; local_got < end_local_got; ++local_got) + if (*local_got > 0) + { + *local_got = htab->sgot->size; + htab->sgot->size += 4; + if (bfd_link_pic (info)) + htab->srelgot->size += sizeof (Elf32_External_Rela); + } + else + *local_got = (bfd_vma) -1; + /* TLS entries of local symbols, in the same array after the GOT counts. */ + { + unsigned int n = elf_tdata (ibfd)->symtab_hdr.sh_info, i; + bfd_signed_vma *refs = elf_local_got_refcounts (ibfd); + for (i = 0; i < n; i++) + { + bfd_signed_vma *g = &refs[I860_LOCAL_GD (n) + i]; + bfd_signed_vma *e = &refs[I860_LOCAL_IE (n) + i]; + if (*g > 0) + { + *g = elf_hash_table (info)->sgot->size; + elf_hash_table (info)->sgot->size += 8; + if (bfd_link_pic (info)) + elf_hash_table (info)->srelgot->size += sizeof (Elf32_External_Rela); + } + else + *g = (bfd_vma) -1; + if (*e > 0) + { + *e = elf_hash_table (info)->sgot->size; + elf_hash_table (info)->sgot->size += 4; + if (bfd_link_pic (info)) + elf_hash_table (info)->srelgot->size += sizeof (Elf32_External_Rela); + } + else + *e = (bfd_vma) -1; + } + } + } + + elf_link_hash_traverse (htab, i860_allocate_dynrelocs, info); + + for (s = dynobj->sections; s != NULL; s = s->next) + { + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + if (s == htab->splt || s == htab->sgot + || s == htab->sgotplt || s == htab->sdynbss + || s == htab->sdynrelro) + ; + else if (startswith (bfd_section_name (s), ".rela")) + { + if (s->size != 0 && s != htab->srelplt) + relocs = true; + s->reloc_count = 0; + } + else + continue; + + if (s->size == 0) + { + s->flags |= SEC_EXCLUDE; + continue; + } + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + + s->contents = bfd_zalloc (dynobj, s->size); + if (s->contents == NULL) + return false; + s->alloced = 1; + } + + return _bfd_elf_add_dynamic_tags (info, relocs); +} + +static bfd_vma +i860_section_addr (asection *s) +{ + return s->output_section->vma + s->output_offset; +} + +static void +i860_append_rela (bfd *output_bfd, asection *srel, Elf_Internal_Rela *rela) +{ + bfd_elf32_swap_reloca_out (output_bfd, rela, + srel->contents + + srel->reloc_count * sizeof (Elf32_External_Rela)); + srel->reloc_count++; +} + +static bool +i860_finish_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + bfd *output_bfd = info->output_bfd; + struct elf_link_hash_table *htab = i860_hash_table (info); + Elf_Internal_Rela rela; + + if (h->plt.offset != (bfd_vma) -1) + { + asection *splt = htab->splt; + asection *sgotplt = htab->sgotplt; + bfd_byte *ent = splt->contents + h->plt.offset; + bfd_vma index = h->plt.offset / PLT_ENTRY_SIZE; + bfd_vma got_offset = (index + GOT_HEADER_WORDS) * 4; + bfd_vma slot = i860_section_addr (sgotplt) + got_offset; + bfd_vma rel = slot - (i860_section_addr (splt) + h->plt.offset + + PLT_PC_OFFSET); + + BFD_ASSERT (h->dynindx != -1); + + bfd_put_32 (output_bfd, PLT_ENTRY_WORD0, ent); + bfd_put_32 (output_bfd, PLT_ENTRY_WORD1, ent + 4); + bfd_put_32 (output_bfd, PLT_ENTRY_WORD2, ent + 8); + bfd_put_32 (output_bfd, PLT_ENTRY_WORD3 | (((rel + 0x8000) >> 16) & 0xffff), + ent + 12); + bfd_put_32 (output_bfd, PLT_ENTRY_WORD4, ent + 16); + bfd_put_32 (output_bfd, PLT_ENTRY_WORD5 | (rel & 0xfffc), ent + 20); + bfd_put_32 (output_bfd, PLT_ENTRY_WORD6, ent + 24); + bfd_put_32 (output_bfd, PLT_ENTRY_WORD7, ent + 28); + + rela.r_offset = slot; + rela.r_info = ELF32_R_INFO (h->dynindx, R_860_JUMP_SLOT); + rela.r_addend = 0; + bfd_elf32_swap_reloca_out (output_bfd, &rela, + htab->srelplt->contents + + index * sizeof (Elf32_External_Rela)); + + if (!h->def_regular) + { + /* A zero value hides the entry from the search for the definition + unless its address has to be the canonical function address. */ + sym->st_shndx = SHN_UNDEF; + if (!h->pointer_equality_needed) + sym->st_value = 0; + } + } + + if (h->got.offset != (bfd_vma) -1) + { + asection *sgot = htab->sgot; + bool local = (bfd_link_pic (info) + && SYMBOL_REFERENCES_LOCAL (info, h)); + + rela.r_offset = i860_section_addr (sgot) + (h->got.offset & ~(bfd_vma) 1); + if (local && h->root.type != bfd_link_hash_undefweak) + { + rela.r_info = ELF32_R_INFO (0, R_860_RELATIVE); + rela.r_addend = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + i860_append_rela (output_bfd, htab->srelgot, &rela); + } + else if (!local) + { + bfd_put_32 (output_bfd, 0, + sgot->contents + (h->got.offset & ~(bfd_vma) 1)); + rela.r_info = ELF32_R_INFO (h->dynindx, R_860_GLOB_DAT); + rela.r_addend = 0; + i860_append_rela (output_bfd, htab->srelgot, &rela); + } + } + + if (h->needs_copy) + { + BFD_ASSERT (h->dynindx != -1 + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)); + + rela.r_offset = (h->root.u.def.value + + i860_section_addr (h->root.u.def.section)); + rela.r_info = ELF32_R_INFO (h->dynindx, R_860_COPY); + rela.r_addend = 0; + i860_append_rela (output_bfd, + (h->root.u.def.section == htab->sdynrelro + ? htab->sreldynrelro : htab->srelbss), + &rela); + } + + if (strcmp (h->root.root.string, "_DYNAMIC") == 0 || h == htab->hgot) + sym->st_shndx = SHN_ABS; + + return true; +} + +static bool +i860_finish_dynamic_sections (struct bfd_link_info *info, + bfd_byte *buf ATTRIBUTE_UNUSED) +{ + bfd *output_bfd = info->output_bfd; + struct elf_link_hash_table *htab = i860_hash_table (info); + bfd *dynobj = htab->dynobj; + asection *sgotplt = htab->sgotplt; + asection *sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); + + if (htab->dynamic_sections_created) + { + Elf32_External_Dyn *dyncon = (Elf32_External_Dyn *) sdyn->contents; + Elf32_External_Dyn *dynconend + = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size); + + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + + bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); + switch (dyn.d_tag) + { + case DT_PLTGOT: + dyn.d_un.d_ptr = i860_section_addr (sgotplt); + break; + case DT_JMPREL: + dyn.d_un.d_ptr = i860_section_addr (htab->srelplt); + break; + case DT_PLTRELSZ: + dyn.d_un.d_val = htab->srelplt->size; + break; + default: + continue; + } + bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); + } + + if (htab->splt != NULL && htab->splt->size > 0) + elf_section_data (htab->splt->output_section)->this_hdr.sh_entsize + = PLT_ENTRY_SIZE; + } + + if (sgotplt != NULL && sgotplt->size > 0) + { + bfd_put_32 (output_bfd, + sdyn != NULL ? i860_section_addr (sdyn) : (bfd_vma) 0, + sgotplt->contents); + elf_section_data (sgotplt->output_section)->this_hdr.sh_entsize = 4; + } + if (htab->sgot != NULL && htab->sgot->size > 0) + elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4; + + return true; +} + +static enum elf_reloc_type_class +i860_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, + const asection *rel_sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *rela) +{ + switch ((int) ELF32_R_TYPE (rela->r_info)) + { + case R_860_RELATIVE: + return reloc_class_relative; + case R_860_JUMP_SLOT: + return reloc_class_plt; + case R_860_COPY: + return reloc_class_copy; + default: + return reloc_class_normal; + } +} + +static bfd_vma +i860_tpoff (struct bfd_link_info *info, bfd_vma address) +{ + asection *tls = elf_hash_table (info)->tls_sec; + + if (tls == NULL) + return 0; + return address - (tls->vma + BFD_ALIGN (elf_hash_table (info)->tls_size, + (bfd_vma) 1 << tls->alignment_power)); +} + +/* The address of the GOT entries at *OFFP, filled on the first use. */ +static bfd_vma +i860_tls_got_entry (bfd *output_bfd, struct bfd_link_info *info, + struct elf_link_hash_entry *h, bfd_vma *offp, + bfd_vma relocation, int gd) +{ + asection *sgot = elf_hash_table (info)->sgot; + asection *tls = elf_hash_table (info)->tls_sec; + bfd_vma off = *offp & ~(bfd_vma) 1; + bfd_vma addr = i860_section_addr (sgot) + off; + bfd_vma dtpoff = tls != NULL ? relocation - tls->vma : 0; + + BFD_ASSERT (*offp != (bfd_vma) -1); + if ((*offp & 1) == 0) + { + int dynsym = i860_tls_dynsym (info, h); + unsigned long sym = dynsym ? h->dynindx : 0; + Elf_Internal_Rela rela; + + *offp |= 1; + rela.r_offset = addr; + rela.r_addend = 0; + if (gd) + { + /* an executable is module 1 */ + bfd_put_32 (output_bfd, dynsym || bfd_link_pic (info) ? 0 : 1, + sgot->contents + off); + bfd_put_32 (output_bfd, dynsym ? 0 : dtpoff, sgot->contents + off + 4); + if (dynsym || bfd_link_pic (info)) + { + rela.r_info = ELF32_R_INFO (sym, R_860_TLS_DTPMOD32); + i860_append_rela (output_bfd, elf_hash_table (info)->srelgot, &rela); + } + if (dynsym) + { + rela.r_offset = addr + 4; + rela.r_info = ELF32_R_INFO (sym, R_860_TLS_DTPOFF32); + i860_append_rela (output_bfd, elf_hash_table (info)->srelgot, &rela); + } + } + else + { + bfd_put_32 (output_bfd, dynsym ? 0 : i860_tpoff (info, relocation), + sgot->contents + off); + if (dynsym || bfd_link_pic (info)) + { + rela.r_info = ELF32_R_INFO (sym, R_860_TLS_TPOFF32); + rela.r_addend = dynsym ? 0 : dtpoff; + i860_append_rela (output_bfd, elf_hash_table (info)->srelgot, &rela); + } + } + } + return addr; +} + +/* Insert VALUE into a GOT, GOT offset or PC relative immediate field. */ +static bfd_reloc_status_type +i860_relocate_pic_field (bfd *abfd, int r_type, bfd_byte *where, bfd_vma value) +{ + bfd_vma insn = bfd_get_32 (abfd, where); + bfd_vma mask = 0xffff; + bool split = false; + + switch (r_type) + { + case R_860_HAGOT: + case R_860_HAGOTOFF: + case R_860_HAPC: + case R_860_TLS_IE_HA: + case R_860_TLS_IE_ABS_HA: + value = (value + 0x8000) >> 16; + break; + case R_860_HIGOT: + case R_860_HIGOTOFF: + case R_860_TLS_GD_HI: + case R_860_TLS_LE_HI: + value >>= 16; + break; + case R_860_LOGOT0: + case R_860_LOGOTOFF0: + case R_860_LOPC: + case R_860_TLS_GD_LO: + case R_860_TLS_LE_LO: + break; + case R_860_LOGOT1: + case R_860_LOGOTOFF1: + case R_860_TLS_IE_LO1: + case R_860_TLS_IE_ABS_LO1: + mask = 0xfffe; + break; + case R_860_LOGOTOFF2: + mask = 0xfffc; + break; + case R_860_LOGOTOFF3: + mask = 0xfff8; + break; + case R_860_SPGOT1: + case R_860_SPGOTOFF1: + mask = 0xfffe; + split = true; + break; + case R_860_SPGOT0: + case R_860_SPGOTOFF0: + split = true; + break; + default: + return bfd_reloc_notsupported; + } + + value &= mask; + if (split) + { + value = ((value & 0xf800) << 5) | (value & 0x7ff); + mask = ((mask & 0xf800) << 5) | (mask & 0x7ff); + } + bfd_put_32 (abfd, (insn & ~mask) | value, where); + return bfd_reloc_ok; +} + +/* The GOT entry of a symbol, relative to _GLOBAL_OFFSET_TABLE_. Fills the + entry unless the dynamic linker does. */ +static bfd_vma +i860_got_offset (bfd *output_bfd, struct bfd_link_info *info, + struct elf_link_hash_table *htab, + struct elf_link_hash_entry *h, bfd_vma *local_got, + bfd_vma relocation) +{ + asection *sgot = htab->sgot; + bfd_vma off; + + if (h != NULL) + { + off = h->got.offset; + BFD_ASSERT (off != (bfd_vma) -1); + if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (htab->dynamic_sections_created, + bfd_link_pic (info), h) + || (bfd_link_pic (info) && SYMBOL_REFERENCES_LOCAL (info, h))) + { + if ((off & 1) == 0) + { + bfd_put_32 (output_bfd, relocation, sgot->contents + off); + h->got.offset |= 1; + } + off &= ~(bfd_vma) 1; + } + } + else + { + off = *local_got; + BFD_ASSERT (off != (bfd_vma) -1); + if ((off & 1) == 0) + { + bfd_put_32 (output_bfd, relocation, sgot->contents + off); + if (bfd_link_pic (info)) + { + Elf_Internal_Rela rela; + + rela.r_offset = i860_section_addr (sgot) + off; + rela.r_info = ELF32_R_INFO (0, R_860_RELATIVE); + rela.r_addend = relocation; + i860_append_rela (output_bfd, htab->srelgot, &rela); + } + *local_got |= 1; + } + off &= ~(bfd_vma) 1; + } + return (i860_section_addr (sgot) + off + - (htab->hgot->root.u.def.value + + i860_section_addr (htab->hgot->root.u.def.section))); +} + +static int +i860_relocate_section (struct bfd_link_info *info, bfd *input_bfd, + asection *input_section, bfd_byte *contents, + Elf_Internal_Rela *relocs, Elf_Internal_Sym *local_syms, + asection **local_sections) +{ + bfd *output_bfd = info->output_bfd; + struct elf_link_hash_table *htab = i860_hash_table (info); + Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); + bfd_vma *local_got = elf_local_got_offsets (input_bfd); + asection *sreloc = elf_section_data (input_section)->sreloc; + Elf_Internal_Rela *relend = relocs + input_section->reloc_count; + Elf_Internal_Rela *rel; + + for (rel = relocs; rel < relend; rel++) + { + reloc_howto_type *howto; + unsigned long r_symndx = ELF32_R_SYM (rel->r_info); + int r_type = ELF32_R_TYPE (rel->r_info); + Elf_Internal_Sym *sym = NULL; + asection *sec = NULL; + struct elf_link_hash_entry *h = NULL; + bfd_vma relocation; + bfd_reloc_status_type r; + const char *name = NULL; + bfd_vma pc; + + howto = lookup_howto ((unsigned) r_type); + if (howto == NULL) + { + /* xgettext:c-format */ + _bfd_error_handler (_("%pB: unsupported relocation type %#x"), + input_bfd, r_type); + bfd_set_error (bfd_error_bad_value); + return false; + } + + if (r_symndx < symtab_hdr->sh_info) + { + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + + name = bfd_elf_string_from_elf_section + (input_bfd, symtab_hdr->sh_link, sym->st_name); + name = (name == NULL) ? bfd_section_name (sec) : name; + } + else + { + bool unresolved_reloc, warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned, ignored); + name = h->root.root.string; + } + + if (sec != NULL && discarded_section (sec)) + RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, + rel, 1, relend, R_860_NONE, + howto, 0, contents); + + if (bfd_link_relocatable (info)) + continue; + + pc = i860_section_addr (input_section) + rel->r_offset; + + switch (r_type) + { + default: + r = i860_final_link_relocate (howto, input_bfd, input_section, + contents, rel, relocation); + break; + + case R_860_32: + if (r_symndx != STN_UNDEF + && (input_section->flags & SEC_ALLOC) != 0 + && ((bfd_link_pic (info) + && (h == NULL || !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))) + || (!bfd_link_pic (info) + && h != NULL + && h->dynindx != -1 + && !h->non_got_ref + && ((h->def_dynamic && !h->def_regular) + || h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined)))) + { + Elf_Internal_Rela outrel; + bfd_vma off = _bfd_elf_section_offset (output_bfd, info, + input_section, + rel->r_offset); + + BFD_ASSERT (sreloc != NULL); + memset (&outrel, 0, sizeof outrel); + if (off != (bfd_vma) -1 && off != (bfd_vma) -2) + { + outrel.r_offset = off + i860_section_addr (input_section); + if (h != NULL && h->dynindx != -1 + && !(bfd_link_pic (info) + && SYMBOL_REFERENCES_LOCAL (info, h))) + { + outrel.r_info = ELF32_R_INFO (h->dynindx, R_860_32); + outrel.r_addend = rel->r_addend; + } + else + { + outrel.r_info = ELF32_R_INFO (0, R_860_RELATIVE); + outrel.r_addend = relocation + rel->r_addend; + } + } + i860_append_rela (output_bfd, sreloc, &outrel); + /* -2: .eh_frame made pc relative, the value goes in place. */ + if (off != (bfd_vma) -2) + continue; + } + r = i860_final_link_relocate (howto, input_bfd, input_section, + contents, rel, relocation); + break; + + case R_860_HIGHADJ: + r = elf32_i860_relocate_highadj (input_bfd, rel, contents, + relocation); + break; + + case R_860_PC16: + r = elf32_i860_relocate_pc16 (input_bfd, input_section, rel, + contents, relocation); + break; + + case R_860_PC26: + case R_860_PLT26: + if (h != NULL && h->plt.offset != (bfd_vma) -1 + && htab->splt != NULL) + relocation = (i860_section_addr (htab->splt) + h->plt.offset); + r = elf32_i860_relocate_pc26 (input_bfd, input_section, rel, + contents, relocation); + break; + + case R_860_SPLIT0: + case R_860_SPLIT1: + case R_860_SPLIT2: + r = elf32_i860_relocate_splitn (input_bfd, rel, contents, + relocation); + break; + + case R_860_LOGOT0: + case R_860_SPGOT0: + case R_860_LOGOT1: + case R_860_SPGOT1: + case R_860_HAGOT: + case R_860_HIGOT: + relocation = i860_got_offset (output_bfd, info, htab, h, + (h == NULL && local_got != NULL + ? &local_got[r_symndx] : NULL), + relocation + (h == NULL ? 0 : rel->r_addend)); + r = i860_relocate_pic_field (input_bfd, r_type, + contents + rel->r_offset, relocation); + break; + + case R_860_LOGOTOFF0: + case R_860_SPGOTOFF0: + case R_860_LOGOTOFF1: + case R_860_SPGOTOFF1: + case R_860_LOGOTOFF2: + case R_860_LOGOTOFF3: + case R_860_HAGOTOFF: + case R_860_HIGOTOFF: + relocation += (rel->r_addend + - (htab->hgot->root.u.def.value + + i860_section_addr + (htab->hgot->root.u.def.section))); + r = i860_relocate_pic_field (input_bfd, r_type, + contents + rel->r_offset, relocation); + break; + + case R_860_LOPC: + case R_860_HAPC: + if (h != NULL && bfd_link_pic (info) + && h != htab->hgot + && !SYMBOL_REFERENCES_LOCAL (info, h)) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%pB: PC relative relocation %s against preemptible " + "symbol `%s'"), + input_bfd, howto->name, name); + bfd_set_error (bfd_error_bad_value); + return false; + } + r = i860_relocate_pic_field (input_bfd, r_type, + contents + rel->r_offset, + relocation + rel->r_addend - pc); + break; + + case R_860_TLS_GD_HI: + case R_860_TLS_GD_LO: + case R_860_TLS_IE_HA: + case R_860_TLS_IE_LO1: + case R_860_TLS_IE_ABS_HA: + case R_860_TLS_IE_ABS_LO1: + { + int gd = r_type == R_860_TLS_GD_HI || r_type == R_860_TLS_GD_LO; + int abs = r_type == R_860_TLS_IE_ABS_HA || r_type == R_860_TLS_IE_ABS_LO1; + struct elf_i860_link_hash_entry *th = (struct elf_i860_link_hash_entry *) h; + unsigned int n = symtab_hdr->sh_info; + bfd_vma *offp; + + if (th != NULL) + offp = gd ? &th->tls_gd_got : &th->tls_ie_got; + else + offp = &local_got[(gd ? I860_LOCAL_GD (n) : I860_LOCAL_IE (n)) + r_symndx]; + relocation = i860_tls_got_entry (output_bfd, info, h, offp, relocation, gd); + if (!abs) + relocation -= (elf_hash_table (info)->hgot->root.u.def.value + + i860_section_addr + (elf_hash_table (info)->hgot->root.u.def.section)); + r = i860_relocate_pic_field (input_bfd, r_type, + contents + rel->r_offset, relocation); + } + break; + + case R_860_TLS_LE_HI: + case R_860_TLS_LE_LO: + r = i860_relocate_pic_field (input_bfd, r_type, contents + rel->r_offset, + i860_tpoff (info, relocation) + rel->r_addend); + break; + + /* Output only relocations. */ + case R_860_TLS_DTPMOD32: + case R_860_TLS_DTPOFF32: + case R_860_TLS_TPOFF32: + case R_860_COPY: + case R_860_GLOB_DAT: + case R_860_JUMP_SLOT: + case R_860_RELATIVE: + r = bfd_reloc_notsupported; + break; + } + + if (r != bfd_reloc_ok) + { + const char *msg = NULL; + + switch (r) + { + case bfd_reloc_overflow: + (*info->callbacks->reloc_overflow) + (info, (h ? &h->root : NULL), name, howto->name, + (bfd_vma) 0, input_bfd, input_section, rel->r_offset); + break; + case bfd_reloc_undefined: + (*info->callbacks->undefined_symbol) + (info, name, input_bfd, input_section, rel->r_offset, true); + break; + case bfd_reloc_outofrange: + msg = _("internal error: out of range error"); + break; + case bfd_reloc_notsupported: + msg = _("internal error: unsupported relocation error"); + break; + case bfd_reloc_dangerous: + msg = _("internal error: dangerous relocation"); + break; + default: + msg = _("internal error: unknown error"); + break; + } + if (msg) + (*info->callbacks->warning) (info, msg, name, input_bfd, + input_section, rel->r_offset); + } + } + return true; +} + +/* Return whether a symbol name implies a local label. SVR4/860 compilers + generate labels of the form ".ep.function_name" to denote the end of a + function prolog. These should be local. + ??? Do any other SVR4 compilers have this convention? If so, this should + be added to the generic routine. */ +static bool +elf32_i860_is_local_label_name (bfd *abfd, const char *name) +{ + if (name[0] == '.' && name[1] == 'e' && name[2] == 'p' && name[3] == '.') + return true; + + return _bfd_elf_is_local_label_name (abfd, name); +} + +#define TARGET_BIG_SYM i860_elf32_vec +#define TARGET_BIG_NAME "elf32-i860" +#define TARGET_LITTLE_SYM i860_elf32_le_vec +#define TARGET_LITTLE_NAME "elf32-i860-little" +#define ELF_ARCH bfd_arch_i860 +#define ELF_MACHINE_CODE EM_860 +#define ELF_MAXPAGESIZE 4096 + +#define elf_backend_rela_normal 1 +#define elf_info_to_howto_rel NULL +#define elf_info_to_howto elf32_i860_info_to_howto_rela +#define elf_backend_relocate_section i860_relocate_section +#define elf_backend_check_relocs i860_check_relocs +#define elf_backend_can_gc_sections 1 +#define elf_backend_can_refcount 1 +#define elf_backend_plt_readonly 1 +#define elf_backend_want_got_plt 1 +#define elf_backend_want_plt_sym 0 +#define elf_backend_got_header_size (GOT_HEADER_WORDS * 4) +#define elf_backend_dtrel_excludes_plt 1 +#define elf_backend_want_dynrelro 1 +#define elf_backend_reloc_type_class i860_reloc_type_class +#define elf_backend_copy_indirect_symbol i860_copy_indirect_symbol +#define elf_backend_create_dynamic_sections _bfd_elf_create_dynamic_sections +#define elf_backend_adjust_dynamic_symbol i860_adjust_dynamic_symbol +#define elf_backend_late_size_sections i860_late_size_sections +#define elf_backend_finish_dynamic_symbol i860_finish_dynamic_symbol +#define elf_backend_finish_dynamic_sections i860_finish_dynamic_sections +#define bfd_elf32_bfd_link_hash_table_create i860_link_hash_table_create +#define bfd_elf32_bfd_reloc_type_lookup elf32_i860_reloc_type_lookup +#define bfd_elf32_bfd_reloc_name_lookup elf32_i860_reloc_name_lookup +#define bfd_elf32_bfd_is_local_label_name elf32_i860_is_local_label_name + +#include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 038f2b56c65..867ed26d180 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -2653,6 +2653,46 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_CRIS_16_TPREL", "BFD_RELOC_CRIS_DTPMOD", "BFD_RELOC_CRIS_32_IE", + "BFD_RELOC_860_COPY", + "BFD_RELOC_860_GLOB_DAT", + "BFD_RELOC_860_JUMP_SLOT", + "BFD_RELOC_860_RELATIVE", + "BFD_RELOC_860_PC26", + "BFD_RELOC_860_PLT26", + "BFD_RELOC_860_PC16", + "BFD_RELOC_860_LOW0", + "BFD_RELOC_860_SPLIT0", + "BFD_RELOC_860_LOW1", + "BFD_RELOC_860_SPLIT1", + "BFD_RELOC_860_LOW2", + "BFD_RELOC_860_SPLIT2", + "BFD_RELOC_860_LOW3", + "BFD_RELOC_860_LOGOT0", + "BFD_RELOC_860_SPGOT0", + "BFD_RELOC_860_LOGOT1", + "BFD_RELOC_860_SPGOT1", + "BFD_RELOC_860_LOGOTOFF0", + "BFD_RELOC_860_SPGOTOFF0", + "BFD_RELOC_860_LOGOTOFF1", + "BFD_RELOC_860_SPGOTOFF1", + "BFD_RELOC_860_LOGOTOFF2", + "BFD_RELOC_860_LOGOTOFF3", + "BFD_RELOC_860_LOPC", + "BFD_RELOC_860_HIGHADJ", + "BFD_RELOC_860_HAGOT", + "BFD_RELOC_860_HAGOTOFF", + "BFD_RELOC_860_HAPC", + "BFD_RELOC_860_HIGH", + "BFD_RELOC_860_HIGOT", + "BFD_RELOC_860_HIGOTOFF", + "BFD_RELOC_860_TLS_GD_HI", + "BFD_RELOC_860_TLS_GD_LO", + "BFD_RELOC_860_TLS_IE_HA", + "BFD_RELOC_860_TLS_IE_LO1", + "BFD_RELOC_860_TLS_IE_ABS_HA", + "BFD_RELOC_860_TLS_IE_ABS_LO1", + "BFD_RELOC_860_TLS_LE_HI", + "BFD_RELOC_860_TLS_LE_LO", "BFD_RELOC_OR1K_REL_26", "BFD_RELOC_OR1K_SLO16", "BFD_RELOC_OR1K_PCREL_PG21", diff --git a/bfd/po/SRC-POTFILES.in b/bfd/po/SRC-POTFILES.in index 5f85b8c1a3c..7feb0fd71c7 100644 --- a/bfd/po/SRC-POTFILES.in +++ b/bfd/po/SRC-POTFILES.in @@ -64,6 +64,7 @@ cpu-h8300.c cpu-h8300.h cpu-hppa.c cpu-i386.c +cpu-i860.c cpu-ia64.c cpu-iamcu.c cpu-ip2k.c @@ -176,6 +177,7 @@ elf32-h8300.c elf32-hppa.c elf32-hppa.h elf32-i386.c +elf32-i860.c elf32-ip2k.c elf32-iq2000.c elf32-lm32.c diff --git a/bfd/reloc.c b/bfd/reloc.c index c7c611fb844..191583d6570 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -1,5 +1,6 @@ /* BFD support for handling relocation entries. Copyright (C) 1990-2026 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe Written by Cygnus Support. This file is part of BFD, the Binary File Descriptor library. @@ -5640,6 +5641,89 @@ ENUMX ENUMDOC Relocs used in TLS code for CRIS. +ENUM + BFD_RELOC_860_COPY +ENUMX + BFD_RELOC_860_GLOB_DAT +ENUMX + BFD_RELOC_860_JUMP_SLOT +ENUMX + BFD_RELOC_860_RELATIVE +ENUMX + BFD_RELOC_860_PC26 +ENUMX + BFD_RELOC_860_PLT26 +ENUMX + BFD_RELOC_860_PC16 +ENUMX + BFD_RELOC_860_LOW0 +ENUMX + BFD_RELOC_860_SPLIT0 +ENUMX + BFD_RELOC_860_LOW1 +ENUMX + BFD_RELOC_860_SPLIT1 +ENUMX + BFD_RELOC_860_LOW2 +ENUMX + BFD_RELOC_860_SPLIT2 +ENUMX + BFD_RELOC_860_LOW3 +ENUMX + BFD_RELOC_860_LOGOT0 +ENUMX + BFD_RELOC_860_SPGOT0 +ENUMX + BFD_RELOC_860_LOGOT1 +ENUMX + BFD_RELOC_860_SPGOT1 +ENUMX + BFD_RELOC_860_LOGOTOFF0 +ENUMX + BFD_RELOC_860_SPGOTOFF0 +ENUMX + BFD_RELOC_860_LOGOTOFF1 +ENUMX + BFD_RELOC_860_SPGOTOFF1 +ENUMX + BFD_RELOC_860_LOGOTOFF2 +ENUMX + BFD_RELOC_860_LOGOTOFF3 +ENUMX + BFD_RELOC_860_LOPC +ENUMX + BFD_RELOC_860_HIGHADJ +ENUMX + BFD_RELOC_860_HAGOT +ENUMX + BFD_RELOC_860_HAGOTOFF +ENUMX + BFD_RELOC_860_HAPC +ENUMX + BFD_RELOC_860_HIGH +ENUMX + BFD_RELOC_860_HIGOT +ENUMX + BFD_RELOC_860_HIGOTOFF +ENUMX + BFD_RELOC_860_TLS_GD_HI +ENUMX + BFD_RELOC_860_TLS_GD_LO +ENUMX + BFD_RELOC_860_TLS_IE_HA +ENUMX + BFD_RELOC_860_TLS_IE_LO1 +ENUMX + BFD_RELOC_860_TLS_IE_ABS_HA +ENUMX + BFD_RELOC_860_TLS_IE_ABS_LO1 +ENUMX + BFD_RELOC_860_TLS_LE_HI +ENUMX + BFD_RELOC_860_TLS_LE_LO +ENUMDOC + Intel i860 Relocations. + ENUM BFD_RELOC_OR1K_REL_26 ENUMX diff --git a/bfd/targets.c b/bfd/targets.c index bc620fd7c60..0375af220d2 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -1,5 +1,6 @@ /* Generic target-file-type support for the BFD library. Copyright (C) 1990-2026 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe Written by Cygnus Support. This file is part of BFD, the Binary File Descriptor library. @@ -758,6 +759,8 @@ extern const bfd_target i386_msdos_vec; extern const bfd_target i386_pe_vec; extern const bfd_target i386_pe_big_vec; extern const bfd_target i386_pei_vec; +extern const bfd_target i860_elf32_vec; +extern const bfd_target i860_elf32_le_vec; extern const bfd_target iamcu_elf32_vec; extern const bfd_target ia64_elf32_be_vec; extern const bfd_target ia64_elf32_hpux_be_vec; @@ -1103,6 +1106,8 @@ static const bfd_target * const _bfd_target_vector[] = &i386_pe_big_vec, &i386_pei_vec, + &i860_elf32_vec, + &i860_elf32_le_vec, &iamcu_elf32_vec, #ifdef BFD64 diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp index 99c74c4fd57..672f19c8cc0 100644 --- a/binutils/testsuite/binutils-all/objdump.exp +++ b/binutils/testsuite/binutils-all/objdump.exp @@ -35,7 +35,7 @@ set got [binutils_run $OBJDUMP "$OBJDUMPFLAGS -i"] set cpus_expected [list] lappend cpus_expected aarch64 alpha am33-2 arc ARC700 ARCv2 arm cris -lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 iamcu ip2022 +lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 iamcu ip2022 lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k MCore mep c5 h1 MicroBlaze lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k lappend cpus_expected or1k or1knd pj powerpc pyramid riscv romp rs6000 s390 sh sparc diff --git a/gas/Makefile.am b/gas/Makefile.am index e124ddb4776..b907cd38170 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -1,6 +1,7 @@ ## Process this file with automake to generate Makefile.in # # Copyright (C) 2012-2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -164,6 +165,7 @@ TARGET_CPU_CFILES = \ config/tc-hppa.c \ config/tc-ia64.c \ config/tc-i386.c \ + config/tc-i860.c \ config/tc-ip2k.c \ config/tc-iq2000.c \ config/tc-kvx.c \ @@ -239,6 +241,7 @@ TARGET_CPU_HFILES = \ config/tc-hppa.h \ config/tc-ia64.h \ config/tc-i386.h \ + config/tc-i860.h \ config/tc-ip2k.h \ config/tc-iq2000.h \ config/tc-kvx.h \ diff --git a/gas/Makefile.in b/gas/Makefile.in index 9554046be0f..7f7cae632aa 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -666,6 +666,7 @@ TARGET_CPU_CFILES = \ config/tc-hppa.c \ config/tc-ia64.c \ config/tc-i386.c \ + config/tc-i860.c \ config/tc-ip2k.c \ config/tc-iq2000.c \ config/tc-kvx.c \ @@ -741,6 +742,7 @@ TARGET_CPU_HFILES = \ config/tc-hppa.h \ config/tc-ia64.h \ config/tc-i386.h \ + config/tc-i860.h \ config/tc-ip2k.h \ config/tc-iq2000.h \ config/tc-kvx.h \ @@ -982,6 +984,7 @@ CPU_DOCS = \ doc/c-h8300.texi \ doc/c-hppa.texi \ doc/c-i386.texi \ + doc/c-i860.texi \ doc/c-ip2k.texi \ doc/c-kvx.texi \ doc/c-lm32.texi \ @@ -1145,6 +1148,8 @@ config/tc-ia64.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-i386.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) +config/tc-i860.$(OBJEXT): config/$(am__dirstamp) \ + config/$(DEPDIR)/$(am__dirstamp) config/tc-ip2k.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-iq2000.$(OBJEXT): config/$(am__dirstamp) \ @@ -1397,6 +1402,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-h8300.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-hppa.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-i386.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-i860.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-ia64.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-ip2k.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-iq2000.Po@am__quote@ diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c new file mode 100644 index 00000000000..a51388700c5 --- /dev/null +++ b/gas/config/tc-i860.c @@ -0,0 +1,1614 @@ +/* tc-i860.c -- Assembler for the Intel i860 architecture. + Copyright (C) 1989-2018 Free Software Foundation, Inc. + + Brought back from the dead and completely reworked + by Jason Eckhardt . + Copyright (C) 2026 René Rebe + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with GAS; see the file COPYING. If not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#include "as.h" +#include "safe-ctype.h" +#include "subsegs.h" +#include "opcode/i860.h" +#include "elf/i860.h" + + +/* The opcode hash table. */ +static htab_t op_hash = NULL; + +/* These characters always start a comment. */ +const char comment_chars[] = "#!/"; + +/* These characters start a comment at the beginning of a line. */ +const char line_comment_chars[] = "#/"; + +const char line_separator_chars[] = ";"; + +/* Characters that can be used to separate the mantissa from the exponent + in floating point numbers. */ +const char EXP_CHARS[] = "eE"; + +/* Characters that indicate this number is a floating point constant. + As in 0f12.456 or 0d1.2345e12. */ +const char FLT_CHARS[] = "rRsSfFdDxXpP"; + +/* Register prefix (depends on syntax). */ +static char reg_prefix; + +#define MAX_FIXUPS 2 + +struct i860_it +{ + const char *error; + unsigned long opcode; + enum expand_type expand; + struct i860_fi + { + expressionS exp; + bfd_reloc_code_real_type reloc; + int pcrel; + valueT fup; + } fi[MAX_FIXUPS]; +} the_insn; + +/* The current fixup count. */ +static int fc; + +static char *i860_expr_end; + +/* Indicates error if a pseudo operation was expanded after a branch. */ +static char last_expand; + +/* If true, then warn if any pseudo operations were expanded. */ +static int target_warn_expand = 0; + +/* If true, then XP support is enabled. */ +static int target_xp = 0; + +/* If true, then Intel syntax is enabled (default to AT&T/SVR4 syntax). */ +static int target_intel_syntax = 0; + + +/* Prototypes. */ +static void i860_process_insn (char *); +static void s_dual (int); +static void s_enddual (int); +static void s_atmp (int); +static void s_align_wrapper (int); +static int i860_get_expression (char *); +static bfd_reloc_code_real_type obtain_reloc_for_imm16 (fixS *, long *); +#ifdef DEBUG_I860 +static void print_insn (struct i860_it *); +#endif + +/* Parse the SVR4 selectors of an immediate: @ha, @h, @l, @plt and + @got, @gotoff or @pc, each of these optionally with @ha, @h or @l. */ +static char * +i860_parse_selector (char *s, valueT *fup) +{ + if (strncasecmp (s, "@gottpoffabs", 12) == 0) + { + *fup |= OP_SEL_GOTTPABS; + s += 12; + } + else if (strncasecmp (s, "@gottpoff", 9) == 0) + { + *fup |= OP_SEL_GOTTP; + s += 9; + } + else if (strncasecmp (s, "@tlsgd", 6) == 0) + { + *fup |= OP_SEL_TLSGD; + s += 6; + } + else if (strncasecmp (s, "@tpoff", 6) == 0) + { + *fup |= OP_SEL_TPOFF; + s += 6; + } + else if (strncasecmp (s, "@gotoff", 7) == 0) + { + *fup |= OP_SEL_GOTOFF; + s += 7; + } + else if (strncasecmp (s, "@got", 4) == 0) + { + *fup |= OP_SEL_GOT; + s += 4; + } + else if (strncasecmp (s, "@plt", 4) == 0) + { + *fup |= OP_SEL_PLT; + return s + 4; + } + else if (strncasecmp (s, "@pc", 3) == 0) + { + *fup |= OP_SEL_PC; + s += 3; + } + + if (strncmp (s, "@ha", 3) == 0) + { + *fup |= OP_SEL_HA; + s += 3; + } + else if (strncmp (s, "@h", 2) == 0) + { + *fup |= OP_SEL_H; + s += 2; + } + else if (strncmp (s, "@l", 2) == 0) + { + *fup |= OP_SEL_L; + s += 2; + } + return s; +} + +int +i860_force_relocation (fixS *fix) +{ + if (fix->fx_addnumber & OP_SEL_PLT) + return 1; + return generic_force_reloc (fix); +} + +/* GOT and PLT entries belong to the symbol, not to a section + offset. */ +int +i860_fix_adjustable (fixS *fix) +{ + return (fix->fx_addnumber & (OP_SEL_GOT | OP_SEL_PLT | OP_SEL_TLSGD | OP_SEL_GOTTP + | OP_SEL_GOTTPABS | OP_SEL_TPOFF)) == 0; +} + +const pseudo_typeS md_pseudo_table[] = +{ + {"align", s_align_wrapper, 0}, + {"dual", s_dual, 0}, + {"enddual", s_enddual, 0}, + {"atmp", s_atmp, 0}, + {NULL, 0, 0}, +}; + +/* Dual-instruction mode handling. */ +enum dual +{ + DUAL_OFF = 0, DUAL_ON, DUAL_DDOT, DUAL_ONDDOT, +}; +static enum dual dual_mode = DUAL_OFF; + +/* Handle ".dual" directive. */ +static void +s_dual (int ignore ATTRIBUTE_UNUSED) +{ + if (target_intel_syntax) + dual_mode = DUAL_ON; + else + as_bad (_("Directive .dual available only with -mintel-syntax option")); +} + +/* Handle ".enddual" directive. */ +static void +s_enddual (int ignore ATTRIBUTE_UNUSED) +{ + if (target_intel_syntax) + dual_mode = DUAL_OFF; + else + as_bad (_("Directive .enddual available only with -mintel-syntax option")); +} + +/* Temporary register used when expanding assembler pseudo operations. */ +static int atmp = 31; + +static void +s_atmp (int ignore ATTRIBUTE_UNUSED) +{ + int temp; + + if (! target_intel_syntax) + { + as_bad (_("Directive .atmp available only with -mintel-syntax option")); + demand_empty_rest_of_line (); + return; + } + + if (strncmp (input_line_pointer, "sp", 2) == 0) + { + input_line_pointer += 2; + atmp = 2; + } + else if (strncmp (input_line_pointer, "fp", 2) == 0) + { + input_line_pointer += 2; + atmp = 3; + } + else if (strncmp (input_line_pointer, "r", 1) == 0) + { + input_line_pointer += 1; + temp = get_absolute_expression (); + if (temp >= 0 && temp <= 31) + atmp = temp; + else + as_bad (_("Unknown temporary pseudo register")); + } + else + { + as_bad (_("Unknown temporary pseudo register")); + } + demand_empty_rest_of_line (); +} + +/* Handle ".align" directive depending on syntax mode. + AT&T/SVR4 syntax uses the standard align directive. However, + the Intel syntax additionally allows keywords for the alignment + parameter: ".align type", where type is one of {.short, .long, + .quad, .single, .double} representing alignments of 2, 4, + 16, 4, and 8, respectively. */ +static void +s_align_wrapper (int arg) +{ + char *parm = input_line_pointer; + + if (target_intel_syntax) + { + /* Replace a keyword with the equivalent integer so the + standard align routine can parse the directive. */ + if (strncmp (parm, ".short", 6) == 0) + memcpy (parm, " 2", 6); + else if (strncmp (parm, ".long", 5) == 0) + memcpy (parm, " 4", 5); + else if (strncmp (parm, ".quad", 5) == 0) + memcpy (parm, " 16", 5); + else if (strncmp (parm, ".single", 7) == 0) + memcpy (parm, " 4", 7); + else if (strncmp (parm, ".double", 7) == 0) + memcpy (parm, " 8", 7); + + while (*input_line_pointer == ' ') + ++input_line_pointer; + } + + s_align_bytes (arg); +} + +/* This function is called once, at assembler startup time. It should + set up all the tables and data structures that the MD part of the + assembler will need. */ +void +md_begin (void) +{ + int lose = 0; + unsigned int i = 0; + + op_hash = str_htab_create (); + + while (i860_opcodes[i].name != NULL) + { + const char *name = i860_opcodes[i].name; + if (str_hash_insert (op_hash, name, &i860_opcodes[i], 0) != NULL) + { + fprintf (stderr, _("internal error: can't hash `%s'\n"), + i860_opcodes[i].name); + lose = 1; + } + do + { + if (i860_opcodes[i].match & i860_opcodes[i].lose) + { + fprintf (stderr, + _("internal error: losing opcode: `%s' \"%s\"\n"), + i860_opcodes[i].name, i860_opcodes[i].args); + lose = 1; + } + ++i; + } + while (i860_opcodes[i].name != NULL + && strcmp (i860_opcodes[i].name, name) == 0); + } + + if (lose) + as_fatal (_("Defective assembler. No assembly attempted.")); + + /* Set the register prefix for either Intel or AT&T/SVR4 syntax. */ + reg_prefix = target_intel_syntax ? 0 : '%'; +} + +/* This is the core of the machine-dependent assembler. STR points to a + machine dependent instruction. This function emits the frags/bytes + it assembles to. */ +/* Addresses are not known yet and a frag can end anywhere: count from the last + alignment of at least 8 bytes, or the start of the section. */ +static int +i860_dual_aligned_p (void) +{ + valueT offset = 0; + fragS *f; + + for (f = frchain_now->frch_root; f != NULL && f != frag_now; f = f->fr_next) + switch (f->fr_type) + { + case rs_align: + case rs_align_code: + if (f->fr_offset >= 3) + offset = 0; + else + return 1; + break; + case rs_fill: + offset += f->fr_fix + f->fr_var * f->fr_offset; + break; + default: + return 1; + } + offset += frag_now_fix_octets (); + return (offset & 7) == 0; +} + +void +md_assemble (char *str) +{ + char *destp; + int num_opcodes = 1; + int i; + struct i860_it pseudo[3]; + + gas_assert (str); + fc = 0; + + /* Assemble the instruction. */ + i860_process_insn (str); + + /* Check for expandable flag to produce pseudo-instructions. This + is an undesirable feature that should be avoided. */ + if (the_insn.expand != 0 && the_insn.expand != XP_ONLY + && ! (the_insn.fi[0].fup & (OP_SEL_HA | OP_SEL_H | OP_SEL_L | OP_SEL_GOT + | OP_SEL_GOTOFF | OP_SEL_PLT | OP_SEL_PC + | OP_SEL_TLSGD | OP_SEL_GOTTP + | OP_SEL_GOTTPABS | OP_SEL_TPOFF))) + { + for (i = 0; i < 3; i++) + pseudo[i] = the_insn; + + fc = 1; + switch (the_insn.expand) + { + + case E_DELAY: + num_opcodes = 1; + break; + + case E_MOV: + if (the_insn.fi[0].exp.X_add_symbol == NULL + && the_insn.fi[0].exp.X_op_symbol == NULL + && (the_insn.fi[0].exp.X_add_number < (1 << 15) + && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) + break; + + /* Emit "or l%const,r0,ireg_dest". */ + pseudo[0].opcode = (the_insn.opcode & 0x001f0000) | 0xe4000000; + pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); + + /* Emit "orh h%const,ireg_dest,ireg_dest". */ + pseudo[1].opcode = (the_insn.opcode & 0x03ffffff) | 0xec000000 + | ((the_insn.opcode & 0x001f0000) << 5); + pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); + + num_opcodes = 2; + break; + + case E_ADDR: + if (the_insn.fi[0].exp.X_add_symbol == NULL + && the_insn.fi[0].exp.X_op_symbol == NULL + && (the_insn.fi[0].exp.X_add_number < (1 << 15) + && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) + break; + + /* Emit "orh ha%addr_expr,ireg_src2,r31". */ + pseudo[0].opcode = 0xec000000 | (the_insn.opcode & 0x03e00000) + | (atmp << 16); + pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_HA); + + /* Emit "l%addr_expr(r31),ireg_dest". We pick up the fixup + information from the original instruction. */ + pseudo[1].opcode = (the_insn.opcode & ~0x03e00000) | (atmp << 21); + pseudo[1].fi[0].fup = the_insn.fi[0].fup | OP_SEL_L; + + num_opcodes = 2; + break; + + case E_U32: + if (the_insn.fi[0].exp.X_add_symbol == NULL + && the_insn.fi[0].exp.X_op_symbol == NULL + && (the_insn.fi[0].exp.X_add_number < (1 << 16) + && the_insn.fi[0].exp.X_add_number >= 0)) + break; + + /* Emit "$(opcode)h h%const,ireg_src2,r31". */ + pseudo[0].opcode = (the_insn.opcode & 0xf3e0ffff) | 0x0c000000 + | (atmp << 16); + pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); + + /* Emit "$(opcode) l%const,r31,ireg_dest". */ + pseudo[1].opcode = (the_insn.opcode & 0xf01f0000) | 0x04000000 + | (atmp << 21); + pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); + + num_opcodes = 2; + break; + + case E_AND: + if (the_insn.fi[0].exp.X_add_symbol == NULL + && the_insn.fi[0].exp.X_op_symbol == NULL + && (the_insn.fi[0].exp.X_add_number < (1 << 16) + && the_insn.fi[0].exp.X_add_number >= 0)) + break; + + /* Emit "andnot h%const,ireg_src2,r31". */ + pseudo[0].opcode = (the_insn.opcode & 0x03e0ffff) | 0xd4000000 + | (atmp << 16); + pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); + pseudo[0].fi[0].exp.X_add_number = + -1 - the_insn.fi[0].exp.X_add_number; + + /* Emit "andnot l%const,r31,ireg_dest". */ + pseudo[1].opcode = (the_insn.opcode & 0x001f0000) | 0xd4000000 + | (atmp << 21); + pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); + pseudo[1].fi[0].exp.X_add_number = + -1 - the_insn.fi[0].exp.X_add_number; + + num_opcodes = 2; + break; + + case E_S32: + if (the_insn.fi[0].exp.X_add_symbol == NULL + && the_insn.fi[0].exp.X_op_symbol == NULL + && (the_insn.fi[0].exp.X_add_number < (1 << 15) + && the_insn.fi[0].exp.X_add_number >= -(1 << 15))) + break; + + /* Emit "orh h%const,r0,r31". */ + pseudo[0].opcode = 0xec000000 | (atmp << 16); + pseudo[0].fi[0].fup = (OP_IMM_S16 | OP_SEL_H); + + /* Emit "or l%const,r31,r31". */ + pseudo[1].opcode = 0xe4000000 | (atmp << 21) | (atmp << 16); + pseudo[1].fi[0].fup = (OP_IMM_S16 | OP_SEL_L); + + /* Emit "r31,ireg_src2,ireg_dest". */ + pseudo[2].opcode = (the_insn.opcode & ~0x0400ffff) | (atmp << 11); + pseudo[2].fi[0].fup = OP_IMM_S16; + + num_opcodes = 3; + break; + + default: + as_fatal (_("failed sanity check.")); + } + + the_insn = pseudo[0]; + + /* Warn if an opcode is expanded after a delayed branch. */ + if (num_opcodes > 1 && last_expand == 1) + as_warn (_("Expanded opcode after delayed branch: `%s'"), str); + + /* Warn if an opcode is expanded in dual mode. */ + if (num_opcodes > 1 && dual_mode != DUAL_OFF) + as_warn (_("Expanded opcode in dual mode: `%s'"), str); + + /* Notify if any expansions happen. */ + if (target_warn_expand && num_opcodes > 1) + as_warn (_("An instruction was expanded (%s)"), str); + } + + dwarf2_emit_insn (0); + i = 0; + do + { + int tmp; + + /* Output the opcode. Note that the i860 always reads instructions + as little-endian data. */ + destp = frag_more (4); + number_to_chars_littleendian (destp, the_insn.opcode, 4); + + /* Check for expanded opcode after branch or in dual mode. */ + last_expand = the_insn.fi[0].pcrel; + + /* Output the symbol-dependent stuff. Only btne and bte will ever + loop more than once here, since only they (possibly) have more + than one fixup. */ + for (tmp = 0; tmp < fc; tmp++) + { + if (the_insn.fi[tmp].fup != OP_NONE) + { + fixS *fix; + fix = fix_new_exp (frag_now, + destp - frag_now->fr_literal, + 4, + &the_insn.fi[tmp].exp, + the_insn.fi[tmp].pcrel, + the_insn.fi[tmp].reloc); + + /* Despite the odd name, this is a scratch field. We use + it to encode operand type information. */ + fix->fx_addnumber = the_insn.fi[tmp].fup; + } + } + the_insn = pseudo[++i]; + } + while (--num_opcodes > 0); + +} + +/* Assemble the instruction pointed to by STR. */ +static void +i860_process_insn (char *str) +{ + char *s; + const char *args; + char c; + struct i860_opcode *insn; + char *args_start; + unsigned long opcode; + unsigned int mask; + int match = 0; + int comma = 0; + +#if 1 /* For compiler warnings. */ + args = 0; + insn = 0; + args_start = 0; + opcode = 0; +#endif + + for (s = str; ISLOWER (*s) || *s == '.' || *s == '3' + || *s == '2' || *s == '1'; ++s) + ; + + switch (*s) + { + case '\0': + break; + + case ',': + comma = 1; + + /*FALLTHROUGH*/ + + case ' ': + *s++ = '\0'; + break; + + default: + as_fatal (_("Unknown opcode: `%s'"), str); + } + + /* Check for dual mode ("d.") opcode prefix. */ + if (strncmp (str, "d.", 2) == 0) + { + if (dual_mode == DUAL_ON) + dual_mode = DUAL_ONDDOT; + else + dual_mode = DUAL_DDOT; + str += 2; + } + + if ((insn = (struct i860_opcode *) str_hash_find (op_hash, str)) == NULL) + { + if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT) + str -= 2; + as_bad (_("Unknown opcode: `%s'"), str); + return; + } + + if (comma) + *--s = ','; + + args_start = s; + for (;;) + { + int t; + opcode = insn->match; + memset (&the_insn, '\0', sizeof (the_insn)); + fc = 0; + for (t = 0; t < MAX_FIXUPS; t++) + { + the_insn.fi[t].reloc = BFD_RELOC_NONE; + the_insn.fi[t].pcrel = 0; + the_insn.fi[t].fup = OP_NONE; + } + + /* Build the opcode, checking as we go that the operands match. */ + for (args = insn->args; ; ++args) + { + if (fc > MAX_FIXUPS) + abort (); + + switch (*args) + { + + /* End of args. */ + case '\0': + if (*s == '\0') + match = 1; + break; + + /* These must match exactly. */ + case '+': + case '(': + case ')': + case ',': + case ' ': + if (*s++ == *args) + continue; + break; + + /* Must be at least one digit. */ + case '#': + if (ISDIGIT (*s++)) + { + while (ISDIGIT (*s)) + ++s; + continue; + } + break; + + /* Next operand must be a register. */ + case '1': + case '2': + case 'd': + /* Check for register prefix if necessary. */ + if (reg_prefix && *s != reg_prefix) + goto error; + else if (reg_prefix) + s++; + + switch (*s) + { + /* Frame pointer. */ + case 'f': + s++; + if (*s++ == 'p') + { + mask = 0x3; + break; + } + goto error; + + /* Stack pointer. */ + case 's': + s++; + if (*s++ == 'p') + { + mask = 0x2; + break; + } + goto error; + + /* Any register r0..r31. */ + case 'r': + s++; + if (!ISDIGIT (c = *s++)) + { + goto error; + } + if (ISDIGIT (*s)) + { + if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) + goto error; + } + else + c -= '0'; + mask = c; + break; + + /* Not this opcode. */ + default: + goto error; + } + + /* Obtained the register, now place it in the opcode. */ + switch (*args) + { + case '1': + opcode |= mask << 11; + continue; + + case '2': + opcode |= mask << 21; + continue; + + case 'd': + opcode |= mask << 16; + continue; + + } + break; + + /* Next operand is a floating point register. */ + case 'e': + case 'f': + case 'g': + /* Check for register prefix if necessary. */ + if (reg_prefix && *s != reg_prefix) + goto error; + else if (reg_prefix) + s++; + + if (*s++ == 'f' && ISDIGIT (*s)) + { + mask = *s++; + if (ISDIGIT (*s)) + { + mask = 10 * (mask - '0') + (*s++ - '0'); + if (mask >= 32) + { + break; + } + } + else + mask -= '0'; + + switch (*args) + { + + case 'e': + opcode |= mask << 11; + continue; + + case 'f': + opcode |= mask << 21; + continue; + + case 'g': + opcode |= mask << 16; + if ((opcode & (1 << 10)) && mask != 0 + && (mask == ((opcode >> 11) & 0x1f))) + as_warn (_("Pipelined instruction: fsrc1 = fdest")); + continue; + } + } + break; + + /* Next operand must be a control register. */ + case 'c': + /* Check for register prefix if necessary. */ + if (reg_prefix && *s != reg_prefix) + goto error; + else if (reg_prefix) + s++; + + if (strncmp (s, "fir", 3) == 0) + { + opcode |= 0x0 << 21; + s += 3; + continue; + } + if (strncmp (s, "psr", 3) == 0) + { + opcode |= 0x1 << 21; + s += 3; + continue; + } + if (strncmp (s, "dirbase", 7) == 0) + { + opcode |= 0x2 << 21; + s += 7; + continue; + } + if (strncmp (s, "db", 2) == 0) + { + opcode |= 0x3 << 21; + s += 2; + continue; + } + if (strncmp (s, "fsr", 3) == 0) + { + opcode |= 0x4 << 21; + s += 3; + continue; + } + if (strncmp (s, "epsr", 4) == 0) + { + opcode |= 0x5 << 21; + s += 4; + continue; + } + /* The remaining control registers are XP only. */ + if (target_xp && strncmp (s, "bear", 4) == 0) + { + opcode |= 0x6 << 21; + s += 4; + continue; + } + if (target_xp && strncmp (s, "ccr", 3) == 0) + { + opcode |= 0x7 << 21; + s += 3; + continue; + } + if (target_xp && strncmp (s, "p0", 2) == 0) + { + opcode |= 0x8 << 21; + s += 2; + continue; + } + if (target_xp && strncmp (s, "p1", 2) == 0) + { + opcode |= 0x9 << 21; + s += 2; + continue; + } + if (target_xp && strncmp (s, "p2", 2) == 0) + { + opcode |= 0xa << 21; + s += 2; + continue; + } + if (target_xp && strncmp (s, "p3", 2) == 0) + { + opcode |= 0xb << 21; + s += 2; + continue; + } + break; + + /* 5-bit immediate in src1. */ + case '5': + if (! i860_get_expression (s)) + { + s = i860_expr_end; + the_insn.fi[fc].fup |= OP_IMM_U5; + fc++; + continue; + } + break; + + /* 26-bit immediate, relative branch (lbroff). */ + case 'l': + the_insn.fi[fc].pcrel = 1; + the_insn.fi[fc].fup |= OP_IMM_BR26; + goto immediate; + + /* 16-bit split immediate, relative branch (sbroff). */ + case 'r': + the_insn.fi[fc].pcrel = 1; + the_insn.fi[fc].fup |= OP_IMM_BR16; + goto immediate; + + /* 16-bit split immediate. */ + case 's': + the_insn.fi[fc].fup |= OP_IMM_SPLIT16; + goto immediate; + + /* 16-bit split immediate, byte aligned (st.b). */ + case 'S': + the_insn.fi[fc].fup |= OP_IMM_SPLIT16; + goto immediate; + + /* 16-bit split immediate, half-word aligned (st.s). */ + case 'T': + the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN2); + goto immediate; + + /* 16-bit split immediate, word aligned (st.l). */ + case 'U': + the_insn.fi[fc].fup |= (OP_IMM_SPLIT16 | OP_ENCODE1 | OP_ALIGN4); + goto immediate; + + /* 16-bit immediate. */ + case 'i': + the_insn.fi[fc].fup |= OP_IMM_S16; + goto immediate; + + /* 16-bit immediate, byte aligned (ld.b). */ + case 'I': + the_insn.fi[fc].fup |= OP_IMM_S16; + goto immediate; + + /* 16-bit immediate, half-word aligned (ld.s). */ + case 'J': + the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN2); + goto immediate; + + /* 16-bit immediate, word aligned (ld.l, {p}fld.l, fst.l). */ + case 'K': + if (insn->name[0] == 'l') + the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE1 | OP_ALIGN4); + else + the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE2 | OP_ALIGN4); + goto immediate; + + /* 16-bit immediate, double-word aligned ({p}fld.d, fst.d). */ + case 'L': + the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN8); + goto immediate; + + /* 16-bit immediate, quad-word aligned (fld.q, fst.q). */ + case 'M': + the_insn.fi[fc].fup |= (OP_IMM_S16 | OP_ENCODE3 | OP_ALIGN16); + + /*FALLTHROUGH*/ + + /* Handle the immediate for either the Intel syntax or + SVR4 syntax. The Intel syntax is "ha%immediate" + whereas SVR4 syntax is "[immediate]@ha". */ + immediate: + if (target_intel_syntax == 0) + { + /* AT&T/SVR4 syntax. */ + if (*s == ' ') + s++; + + /* Note that if i860_get_expression() fails, we will still + have created U entries in the symbol table for the + 'symbols' in the input string. Try not to create U + symbols for registers, etc. */ + if (! i860_get_expression (s)) + s = i860_expr_end; + else + goto error; + + s = i860_parse_selector (s, &the_insn.fi[fc].fup); + + the_insn.expand = insn->expand; + fc++; + + continue; + } + else + { + /* Intel syntax. */ + if (*s == ' ') + s++; + if (strncmp (s, "ha%", 3) == 0) + { + the_insn.fi[fc].fup |= OP_SEL_HA; + s += 3; + } + else if (strncmp (s, "h%", 2) == 0) + { + the_insn.fi[fc].fup |= OP_SEL_H; + s += 2; + } + else if (strncmp (s, "l%", 2) == 0) + { + the_insn.fi[fc].fup |= OP_SEL_L; + s += 2; + } + the_insn.expand = insn->expand; + + /* Note that if i860_get_expression() fails, we will still + have created U entries in the symbol table for the + 'symbols' in the input string. Try not to create U + symbols for registers, etc. */ + if (! i860_get_expression (s)) + s = i860_expr_end; + else + goto error; + + fc++; + continue; + } + break; + + default: + as_fatal (_("failed sanity check.")); + } + break; + } + error: + if (match == 0) + { + /* Args don't match. */ + if (insn[1].name != NULL + && ! strcmp (insn->name, insn[1].name)) + { + ++insn; + s = args_start; + continue; + } + else + { + as_bad (_("Illegal operands for %s"), insn->name); + return; + } + } + break; + } + + /* Set the dual bit on this instruction if necessary. */ + if (dual_mode != DUAL_OFF) + { + if ((opcode & 0xfc000000) == 0x48000000 || opcode == 0xb0000000) + { + /* The instruction is a flop or a fnop, so set its dual bit + (but check that it is 8-byte aligned). */ + if (i860_dual_aligned_p ()) + opcode |= (1 << 9); + else + as_bad (_("'d.%s' must be 8-byte aligned"), insn->name); + + if (dual_mode == DUAL_DDOT) + dual_mode = DUAL_OFF; + else if (dual_mode == DUAL_ONDDOT) + dual_mode = DUAL_ON; + } + else if (dual_mode == DUAL_DDOT || dual_mode == DUAL_ONDDOT) + as_bad (_("Prefix 'd.' invalid for instruction `%s'"), insn->name); + } + + the_insn.opcode = opcode; + + /* Only recognize XP instructions when the user has requested it. */ + if (insn->expand == XP_ONLY && ! target_xp) + as_bad (_("Unknown opcode: `%s'"), insn->name); +} + +static int +i860_get_expression (char *str) +{ + char *save_in; + segT seg; + + save_in = input_line_pointer; + input_line_pointer = str; + seg = expression (&the_insn.fi[fc].exp); + if (seg != absolute_section + && seg != undefined_section + && ! SEG_NORMAL (seg)) + { + the_insn.error = _("bad segment"); + i860_expr_end = input_line_pointer; + input_line_pointer = save_in; + return 1; + } + i860_expr_end = input_line_pointer; + input_line_pointer = save_in; + return 0; +} + +const char * +md_atof (int type, char *litP, int *sizeP) +{ + return ieee_md_atof (type, litP, sizeP, true); +} + +/* Write out in current endian mode. */ +void +md_number_to_chars (char *buf, valueT val, int n) +{ + if (target_big_endian) + number_to_chars_bigendian (buf, val, n); + else + number_to_chars_littleendian (buf, val, n); +} + +/* This should never be called for i860. */ +int +md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED, + segT segtype ATTRIBUTE_UNUSED) +{ + as_fatal (_("relaxation not supported\n")); +} + +#ifdef DEBUG_I860 +static void +print_insn (struct i860_it *insn) +{ + if (insn->error) + fprintf (stderr, "ERROR: %s\n", insn->error); + + fprintf (stderr, "opcode = 0x%08lx\t", insn->opcode); + fprintf (stderr, "expand = 0x%x\t", insn->expand); + fprintf (stderr, "reloc = %s\t\n", + bfd_get_reloc_code_name (insn->reloc)); + fprintf (stderr, "exp = {\n"); + fprintf (stderr, "\t\tX_add_symbol = %s\n", + insn->exp.X_add_symbol ? + (S_GET_NAME (insn->exp.X_add_symbol) ? + S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0"); + fprintf (stderr, "\t\tX_op_symbol = %s\n", + insn->exp.X_op_symbol ? + (S_GET_NAME (insn->exp.X_op_symbol) ? + S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0"); + fprintf (stderr, "\t\tX_add_number = %lx\n", + insn->exp.X_add_number); + fprintf (stderr, "}\n"); +} +#endif /* DEBUG_I860 */ + + +#ifdef OBJ_ELF +const char md_shortopts[] = "VQ:"; +#else +const char md_shortopts[] = ""; +#endif + +#define OPTION_EB (OPTION_MD_BASE + 0) +#define OPTION_EL (OPTION_MD_BASE + 1) +#define OPTION_WARN_EXPAND (OPTION_MD_BASE + 2) +#define OPTION_XP (OPTION_MD_BASE + 3) +#define OPTION_INTEL_SYNTAX (OPTION_MD_BASE + 4) + +const struct option md_longopts[] = { + { "EB", no_argument, NULL, OPTION_EB }, + { "EL", no_argument, NULL, OPTION_EL }, + { "mwarn-expand", no_argument, NULL, OPTION_WARN_EXPAND }, + { "mxp", no_argument, NULL, OPTION_XP }, + { "mintel-syntax",no_argument, NULL, OPTION_INTEL_SYNTAX }, + { NULL, no_argument, NULL, 0 } +}; +const size_t md_longopts_size = sizeof (md_longopts); + +int +md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) +{ + switch (c) + { + case OPTION_EB: + target_big_endian = 1; + break; + + case OPTION_EL: + target_big_endian = 0; + break; + + case OPTION_WARN_EXPAND: + target_warn_expand = 1; + break; + + case OPTION_XP: + target_xp = 1; + break; + + case OPTION_INTEL_SYNTAX: + target_intel_syntax = 1; + break; + +#ifdef OBJ_ELF + /* SVR4 argument compatibility (-V): print version ID. */ + case 'V': + print_version_id (); + break; + + /* SVR4 argument compatibility (-Qy, -Qn): controls whether + a .comment section should be emitted or not (ignored). */ + case 'Q': + break; +#endif + + default: + return 0; + } + + return 1; +} + +void +md_show_usage (FILE *stream) +{ + fprintf (stream, _("\ + -EL generate code for little endian mode (default)\n\ + -EB generate code for big endian mode\n\ + -mwarn-expand warn if pseudo operations are expanded\n\ + -mxp enable i860XP support (disabled by default)\n\ + -mintel-syntax enable Intel syntax (default to AT&T/SVR4)\n")); +#ifdef OBJ_ELF + /* SVR4 compatibility flags. */ + fprintf (stream, _("\ + -V print assembler version number\n\ + -Qy, -Qn ignored\n")); +#endif +} + + +/* We have no need to default values of symbols. */ +symbolS * +md_undefined_symbol (char *name ATTRIBUTE_UNUSED) +{ + return 0; +} + +/* The i860 denotes auto-increment with '++'. */ +void +md_operand (expressionS *exp) +{ + char *s; + + for (s = input_line_pointer; *s; s++) + { + if (s[0] == '+' && s[1] == '+') + { + input_line_pointer += 2; + exp->X_op = O_register; + break; + } + } +} + +/* Round up a section size to the appropriate boundary. */ +valueT +md_section_align (segT segment ATTRIBUTE_UNUSED, + valueT size ATTRIBUTE_UNUSED) +{ + /* Byte alignment is fine. */ + return size; +} + +/* On the i860, a PC-relative offset is relative to the address of the + offset plus its size. */ +long +md_pcrel_from (fixS *fixP) +{ + return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; +} + +/* Determine the relocation needed for non PC-relative 16-bit immediates. + Also adjust the given immediate as necessary. Finally, check that + all constraints (such as alignment) are satisfied. */ +static bfd_reloc_code_real_type +obtain_reloc_for_imm16 (fixS *fix, long *val) +{ + valueT fup = fix->fx_addnumber; + bfd_reloc_code_real_type reloc; + + if (fix->fx_pcrel) + abort (); + + /* TLS selectors make the symbol thread local, also if undefined here. */ + if (fup & (OP_SEL_TLSGD | OP_SEL_GOTTP | OP_SEL_GOTTPABS | OP_SEL_TPOFF)) + { + if (fix->fx_addsy) + S_SET_THREAD_LOCAL (fix->fx_addsy); + if (fup & OP_SEL_TLSGD) + return (fup & OP_SEL_H) ? BFD_RELOC_860_TLS_GD_HI : BFD_RELOC_860_TLS_GD_LO; + if (fup & OP_SEL_GOTTP) + return (fup & OP_SEL_HA) ? BFD_RELOC_860_TLS_IE_HA : BFD_RELOC_860_TLS_IE_LO1; + if (fup & OP_SEL_GOTTPABS) + return ((fup & OP_SEL_HA) ? BFD_RELOC_860_TLS_IE_ABS_HA + : BFD_RELOC_860_TLS_IE_ABS_LO1); + return (fup & OP_SEL_H) ? BFD_RELOC_860_TLS_LE_HI : BFD_RELOC_860_TLS_LE_LO; + } + + /* The PIC selectors only name a relocation, the symbol is always kept. */ + if (fup & OP_SEL_PC) + return (fup & OP_SEL_HA) ? BFD_RELOC_860_HAPC : BFD_RELOC_860_LOPC; + if (fup & OP_SEL_GOT) + { + if (fup & OP_SEL_HA) + return BFD_RELOC_860_HAGOT; + if (fup & OP_SEL_H) + return BFD_RELOC_860_HIGOT; + if (fup & OP_IMM_SPLIT16) + return (fup & OP_ENCODE1) ? BFD_RELOC_860_SPGOT1 : BFD_RELOC_860_SPGOT0; + return (fup & OP_ENCODE1) ? BFD_RELOC_860_LOGOT1 : BFD_RELOC_860_LOGOT0; + } + if (fup & OP_SEL_GOTOFF) + { + if (fup & OP_SEL_HA) + return BFD_RELOC_860_HAGOTOFF; + if (fup & OP_SEL_H) + return BFD_RELOC_860_HIGOTOFF; + if (fup & OP_IMM_SPLIT16) + return ((fup & OP_ENCODE1) ? BFD_RELOC_860_SPGOTOFF1 + : BFD_RELOC_860_SPGOTOFF0); + if (fup & OP_ENCODE3) + return BFD_RELOC_860_LOGOTOFF3; + if (fup & OP_ENCODE2) + return BFD_RELOC_860_LOGOTOFF2; + return ((fup & OP_ENCODE1) ? BFD_RELOC_860_LOGOTOFF1 + : BFD_RELOC_860_LOGOTOFF0); + } + + /* Check alignment restrictions. */ + if ((fup & OP_ALIGN2) && (*val & 0x1)) + as_bad_where (fix->fx_file, fix->fx_line, + _("This immediate requires 0 MOD 2 alignment")); + else if ((fup & OP_ALIGN4) && (*val & 0x3)) + as_bad_where (fix->fx_file, fix->fx_line, + _("This immediate requires 0 MOD 4 alignment")); + else if ((fup & OP_ALIGN8) && (*val & 0x7)) + as_bad_where (fix->fx_file, fix->fx_line, + _("This immediate requires 0 MOD 8 alignment")); + else if ((fup & OP_ALIGN16) && (*val & 0xf)) + as_bad_where (fix->fx_file, fix->fx_line, + _("This immediate requires 0 MOD 16 alignment")); + + if (fup & OP_SEL_HA) + { + *val = (*val >> 16) + (*val & 0x8000 ? 1 : 0); + reloc = BFD_RELOC_860_HIGHADJ; + } + else if (fup & OP_SEL_H) + { + *val >>= 16; + reloc = BFD_RELOC_860_HIGH; + } + else if (fup & OP_SEL_L) + { + int num_encode; + if (fup & OP_IMM_SPLIT16) + { + if (fup & OP_ENCODE1) + { + num_encode = 1; + reloc = BFD_RELOC_860_SPLIT1; + } + else if (fup & OP_ENCODE2) + { + num_encode = 2; + reloc = BFD_RELOC_860_SPLIT2; + } + else + { + num_encode = 0; + reloc = BFD_RELOC_860_SPLIT0; + } + } + else + { + if (fup & OP_ENCODE1) + { + num_encode = 1; + reloc = BFD_RELOC_860_LOW1; + } + else if (fup & OP_ENCODE2) + { + num_encode = 2; + reloc = BFD_RELOC_860_LOW2; + } + else if (fup & OP_ENCODE3) + { + num_encode = 3; + reloc = BFD_RELOC_860_LOW3; + } + else + { + num_encode = 0; + reloc = BFD_RELOC_860_LOW0; + } + } + + /* Preserve size encode bits. */ + *val &= ~((1 << num_encode) - 1); + } + else + { + /* No selector. What reloc do we generate (???)? */ + reloc = BFD_RELOC_32; + } + + return reloc; +} + +/* Attempt to simplify or eliminate a fixup. To indicate that a fixup + has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL, + we will have to generate a reloc entry. */ + +void +md_apply_fix (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED) +{ + char *buf; + long val = *valP; + unsigned long insn; + valueT fup; + + buf = fix->fx_frag->fr_literal + fix->fx_where; + + /* We stored a fix-up in this oddly-named scratch field. */ + fup = fix->fx_addnumber; + + /* Recall that earlier we stored the opcode little-endian. Data fix-ups + have no opcode and can be smaller than a word. */ + insn = fup != OP_NONE ? bfd_getl32 (buf) : 0; + + /* Determine the necessary relocations as well as inserting an + immediate into the instruction. */ + if (fup & OP_IMM_U5) + { + if (val & ~0x1f) + as_bad_where (fix->fx_file, fix->fx_line, + _("5-bit immediate too large")); + if (fix->fx_addsy) + as_bad_where (fix->fx_file, fix->fx_line, + _("5-bit field must be absolute")); + + insn |= (val & 0x1f) << 11; + bfd_putl32 (insn, buf); + fix->fx_r_type = BFD_RELOC_NONE; + fix->fx_done = 1; + } + else if (fup & OP_IMM_S16) + { + fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); + + /* Insert the immediate. */ + if (fix->fx_addsy) + fix->fx_done = 0; + else + { + insn |= val & 0xffff; + bfd_putl32 (insn, buf); + fix->fx_r_type = BFD_RELOC_NONE; + fix->fx_done = 1; + } + } + else if (fup & OP_IMM_U16) + abort (); + + else if (fup & OP_IMM_SPLIT16) + { + fix->fx_r_type = obtain_reloc_for_imm16 (fix, &val); + + /* Insert the immediate. */ + if (fix->fx_addsy) + fix->fx_done = 0; + else + { + insn |= val & 0x7ff; + insn |= (val & 0xf800) << 5; + bfd_putl32 (insn, buf); + fix->fx_r_type = BFD_RELOC_NONE; + fix->fx_done = 1; + } + } + else if (fup & OP_IMM_BR16) + { + if (val & 0x3) + as_bad_where (fix->fx_file, fix->fx_line, + _("A branch offset requires 0 MOD 4 alignment")); + + val = val >> 2; + + /* Insert the immediate. */ + if (fix->fx_addsy) + { + fix->fx_done = 0; + fix->fx_r_type = BFD_RELOC_860_PC16; + } + else + { + insn |= (val & 0x7ff); + insn |= ((val & 0xf800) << 5); + bfd_putl32 (insn, buf); + fix->fx_r_type = BFD_RELOC_NONE; + fix->fx_done = 1; + } + } + else if (fup & OP_IMM_BR26) + { + if (val & 0x3) + as_bad_where (fix->fx_file, fix->fx_line, + _("A branch offset requires 0 MOD 4 alignment")); + + val >>= 2; + + /* Insert the immediate. */ + if (fix->fx_addsy) + { + fix->fx_r_type = (fup & OP_SEL_PLT) ? BFD_RELOC_860_PLT26 + : BFD_RELOC_860_PC26; + fix->fx_done = 0; + } + else + { + insn |= (val & 0x3ffffff); + bfd_putl32 (insn, buf); + fix->fx_r_type = BFD_RELOC_NONE; + fix->fx_done = 1; + } + } + else if (fup != OP_NONE) + { + as_bad_where (fix->fx_file, fix->fx_line, + _("Unrecognized fix-up (0x%08lx)"), (unsigned long) fup); + abort (); + } + else + { + /* I believe only fix-ups such as ".long .ep.main-main+0xc8000000" + reach here (???). */ + if (fix->fx_addsy) + { + if (fix->fx_size != 4) + as_bad_where (fix->fx_file, fix->fx_line, + _("no %d byte data relocation"), fix->fx_size); + fix->fx_r_type = BFD_RELOC_32; + fix->fx_done = 0; + } + else + { + md_number_to_chars (buf, val, fix->fx_size); + fix->fx_r_type = BFD_RELOC_NONE; + fix->fx_done = 1; + } + } +} + +/* Generate a machine dependent reloc from a fixup. */ +arelent* +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, + fixS *fixp) +{ + arelent *reloc; + + reloc = XNEW (arelent); + reloc->sym_ptr_ptr = XNEW (asymbol *); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc->addend = fixp->fx_offset; + reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); + + if (! reloc->howto) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + "Cannot represent %s relocation in object file", + bfd_get_reloc_code_name (fixp->fx_r_type)); + } + return reloc; +} + +/* This is called from HANDLE_ALIGN in write.c. Fill in the contents + of an rs_align_code fragment. */ + +void +i860_handle_align (fragS *fragp) +{ + /* Instructions are always stored little-endian on the i860. */ + static const unsigned char le_nop[] = { 0x00, 0x00, 0x00, 0xA0 }; + + int bytes; + char *p; + + if (fragp->fr_type != rs_align_code) + return; + + bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; + p = fragp->fr_literal + fragp->fr_fix; + + /* Make sure we are on a 4-byte boundary, in case someone has been + putting data into a text section. */ + if (bytes & 3) + { + int fix = bytes & 3; + memset (p, 0, fix); + p += fix; + fragp->fr_fix += fix; + } + + memcpy (p, le_nop, 4); + fragp->fr_var = 4; +} + +/* This is called after a user-defined label is seen. We check + if the label has a double colon (valid in Intel syntax mode only), + in which case it should be externalized. */ + +void +i860_check_label (symbolS *labelsym) +{ + /* At this point, the current line pointer is sitting on the character + just after the first colon on the label. */ + if (target_intel_syntax && *input_line_pointer == ':') + { + S_SET_EXTERNAL (labelsym); + input_line_pointer++; + } +} diff --git a/gas/config/tc-i860.h b/gas/config/tc-i860.h new file mode 100644 index 00000000000..c6592511618 --- /dev/null +++ b/gas/config/tc-i860.h @@ -0,0 +1,101 @@ +/* tc-i860.h -- Header file for the i860. + Copyright (C) 1991-2018 Free Software Foundation, Inc. + + Brought back from the dead and completely reworked + by Jason Eckhardt . + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with GAS; see the file COPYING. If not, write to the Free Software + Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef TC_I860 +#define TC_I860 1 + +enum i860_fix_info +{ + OP_NONE = 0x00000, + OP_IMM_U5 = 0x00001, + OP_IMM_S16 = 0x00002, + OP_IMM_U16 = 0x00004, + OP_IMM_SPLIT16 = 0x00008, + OP_IMM_BR26 = 0x00010, + OP_IMM_BR16 = 0x00020, + OP_ENCODE1 = 0x00040, + OP_ENCODE2 = 0x00080, + OP_ENCODE3 = 0x00100, + OP_SEL_HA = 0x00200, + OP_SEL_H = 0x00400, + OP_SEL_L = 0x00800, + OP_SEL_GOT = 0x01000, + OP_SEL_GOTOFF = 0x02000, + OP_SEL_PLT = 0x04000, + OP_ALIGN2 = 0x08000, + OP_ALIGN4 = 0x10000, + OP_ALIGN8 = 0x20000, + OP_ALIGN16 = 0x40000, + OP_SEL_PC = 0x80000, + OP_SEL_TLSGD = 0x100000, + OP_SEL_GOTTP = 0x200000, + OP_SEL_GOTTPABS = 0x400000, + OP_SEL_TPOFF = 0x800000 +}; + +/* Set the endianness we are using. Default to little endian. */ +#ifndef TARGET_BYTES_BIG_ENDIAN +#define TARGET_BYTES_BIG_ENDIAN 0 +#endif + +/* Whether or not the target is big endian. */ +extern int target_big_endian; + +/* BFD target architecture. */ +#define TARGET_ARCH bfd_arch_i860 + +/* The target BFD format. */ +#ifdef OBJ_ELF +#define TARGET_FORMAT (target_big_endian ? "elf32-i860" : "elf32-i860-little") +#else +#error i860 GAS currently supports only the ELF object format +#endif + +#define WORKING_DOT_WORD +#define DIFF_EXPR_OK + +/* Permit temporary numeric labels. */ +#define LOCAL_LABELS_FB 1 +#define LISTING_HEADER "GAS for i860" + +#define md_convert_frag(b,s,f) abort () + +/* Values passed to md_apply_fix don't include the symbol value. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +extern int i860_force_relocation (struct fix *); +#define TC_FORCE_RELOCATION(FIX) i860_force_relocation (FIX) +extern int i860_fix_adjustable (struct fix *); +#define tc_fix_adjustable(FIX) i860_fix_adjustable (FIX) + +/* Bits for post-processing of a user defined label to check if + it has a double colon (Intel syntax only). */ +extern void i860_check_label (symbolS *labelsym); +#define tc_check_label(ls) i860_check_label (ls) + +/* Bits for filling in rs_align_code fragments with NOPs. */ +extern void i860_handle_align (struct frag *); +#define HANDLE_ALIGN(sec, fragp) i860_handle_align (fragp) + +#define MAX_MEM_FOR_RS_ALIGN_CODE(p2align, max) (3 + 4 + 4) + +#endif /* TC_I860 */ diff --git a/gas/configure.tgt b/gas/configure.tgt index ba3d1194ae9..f78b1ad7d17 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -1,6 +1,7 @@ # gas target specific configuration file. This is a -*- sh -*- file. # # Copyright (C) 2012-2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -269,6 +270,7 @@ case ${generic_target} in ia16-*-elf*) fmt=elf ;; + i860-*-*) fmt=elf endian=little ;; ia64-*-elf*) fmt=elf ;; ia64-*-*vms*) fmt=elf em=vms ;; ia64-*-linux-*) fmt=elf em=linux ;; diff --git a/gas/doc/all.texi b/gas/doc/all.texi index 83418951b13..ccf5603e4d8 100644 --- a/gas/doc/all.texi +++ b/gas/doc/all.texi @@ -41,6 +41,7 @@ @set HPPA @set I370 @set I80386 +@set I860 @set IA64 @set IP2K @set KVX diff --git a/gas/doc/as.texi b/gas/doc/as.texi index c43d48b000f..7e0fc8c6fc3 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -4803,7 +4803,7 @@ required alignment; this can be useful if you want the alignment to be filled with no-op instructions when appropriate. The way the required alignment is specified varies from system to system. -For the arc, hppa, i386 using ELF, iq2000, m68k, or1k, +For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k, s390, sparc, tic4x and xtensa, the first expression is the alignment request in bytes. For example @samp{.align 8} advances the location counter until it is a multiple of 8. If the location counter @@ -8349,6 +8349,9 @@ subject, see the hardware manufacturer's manual. @ifset I80386 * i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features @end ifset +@ifset I860 +* i860-Dependent:: Intel 80860 Dependent Features +@end ifset @ifset IA64 * IA-64-Dependent:: Intel IA-64 Dependent Features @end ifset @@ -8570,6 +8573,10 @@ family. @include c-i386.texi @end ifset +@ifset I860 +@include c-i860.texi +@end ifset + @ifset IA64 @include c-ia64.texi @end ifset diff --git a/gas/doc/c-i860.texi b/gas/doc/c-i860.texi new file mode 100644 index 00000000000..6e6726b965b --- /dev/null +++ b/gas/doc/c-i860.texi @@ -0,0 +1,197 @@ +@c Copyright (C) 2000-2018 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC +@page +@node i860-Dependent +@chapter Intel i860 Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter Intel i860 Dependent Features +@end ifclear + +@ignore +@c FIXME: This is basically a stub for i860. There is tons more information +that I will add later (jle@cygnus.com). +@end ignore + +@cindex i860 support +@menu +* Notes-i860:: i860 Notes +* Options-i860:: i860 Command-line Options +* Directives-i860:: i860 Machine Directives +* Opcodes for i860:: i860 Opcodes +* Syntax of i860:: i860 Syntax +@end menu + +@node Notes-i860 +@section i860 Notes +This is a fairly complete i860 assembler which is compatible with the +UNIX System V/860 Release 4 assembler. However, it does not currently +support SVR4 PIC (i.e., @code{@@GOT, @@GOTOFF, @@PLT}). + +Like the SVR4/860 assembler, the output object format is ELF32. Currently, +this is the only supported object format. If there is sufficient interest, +other formats such as COFF may be implemented. + +Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter +being the default. One difference is that AT&T syntax requires the '%' +prefix on register names while Intel syntax does not. Another difference +is in the specification of relocatable expressions. The Intel syntax +is @code{ha%expression} whereas the SVR4 syntax is @code{[expression]@@ha} +(and similarly for the "l" and "h" selectors). +@node Options-i860 +@section i860 Command-line Options +@subsection SVR4 compatibility options +@table @code +@item -V +Print assembler version. +@item -Qy +Ignored. +@item -Qn +Ignored. +@end table +@subsection Other options +@table @code +@item -EL +Select little endian output (this is the default). +@item -EB +Select big endian output. Note that the i860 always reads instructions +as little endian data, so this option only effects data and not +instructions. +@item -mwarn-expand +Emit a warning message if any pseudo-instruction expansions occurred. +For example, a @code{or} instruction with an immediate larger than 16-bits +will be expanded into two instructions. This is a very undesirable feature to +rely on, so this flag can help detect any code where it happens. One +use of it, for instance, has been to find and eliminate any place +where @code{gcc} may emit these pseudo-instructions. +@item -mxp +Enable support for the i860XP instructions and control registers. By default, +this option is disabled so that only the base instruction set (i.e., i860XR) +is supported. +@item -mintel-syntax +The i860 assembler defaults to AT&T/SVR4 syntax. This option enables the +Intel syntax. +@end table + +@node Directives-i860 +@section i860 Machine Directives + +@cindex machine directives, i860 +@cindex i860 machine directives + +@table @code +@cindex @code{dual} directive, i860 +@item .dual +Enter dual instruction mode. While this directive is supported, the +preferred way to use dual instruction mode is to explicitly code +the dual bit with the @code{d.} prefix. +@end table + +@table @code +@cindex @code{enddual} directive, i860 +@item .enddual +Exit dual instruction mode. While this directive is supported, the +preferred way to use dual instruction mode is to explicitly code +the dual bit with the @code{d.} prefix. +@end table + +@table @code +@cindex @code{atmp} directive, i860 +@item .atmp +Change the temporary register used when expanding pseudo operations. The +default register is @code{r31}. +@end table + +The @code{.dual}, @code{.enddual}, and @code{.atmp} directives are available only in the Intel syntax mode. + +Both syntaxes allow for the standard @code{.align} directive. However, +the Intel syntax additionally allows keywords for the alignment +parameter: "@code{.align type}", where `type' is one of @code{.short}, @code{.long}, +@code{.quad}, @code{.single}, @code{.double} representing alignments of 2, 4, +16, 4, and 8, respectively. + +@node Opcodes for i860 +@section i860 Opcodes + +@cindex opcodes, i860 +@cindex i860 opcodes +All of the Intel i860XR and i860XP machine instructions are supported. Please see +either @emph{i860 Microprocessor Programmer's Reference Manual} or @emph{i860 Microprocessor Architecture} for more information. +@subsection Other instruction support (pseudo-instructions) +For compatibility with some other i860 assemblers, a number of +pseudo-instructions are supported. While these are supported, they are +a very undesirable feature that should be avoided -- in particular, when +they result in an expansion to multiple actual i860 instructions. Below +are the pseudo-instructions that result in expansions. +@itemize @bullet +@item Load large immediate into general register: + +The pseudo-instruction @code{mov imm,%rn} (where the immediate does +not fit within a signed 16-bit field) will be expanded into: +@smallexample +orh large_imm@@h,%r0,%rn +or large_imm@@l,%rn,%rn +@end smallexample +@item Load/store with relocatable address expression: + +For example, the pseudo-instruction @code{ld.b addr_exp(%rx),%rn} +will be expanded into: +@smallexample +orh addr_exp@@ha,%rx,%r31 +ld.l addr_exp@@l(%r31),%rn +@end smallexample + +The analogous expansions apply to @code{ld.x, st.x, fld.x, pfld.x, fst.x}, and @code{pst.x} as well. +@item Signed large immediate with add/subtract: + +If any of the arithmetic operations @code{adds, addu, subs, subu} are used +with an immediate larger than 16-bits (signed), then they will be expanded. +For instance, the pseudo-instruction @code{adds large_imm,%rx,%rn} expands to: +@smallexample +orh large_imm@@h,%r0,%r31 +or large_imm@@l,%r31,%r31 +adds %r31,%rx,%rn +@end smallexample +@item Unsigned large immediate with logical operations: + +Logical operations (@code{or, andnot, or, xor}) also result in expansions. +The pseudo-instruction @code{or large_imm,%rx,%rn} results in: +@smallexample +orh large_imm@@h,%rx,%r31 +or large_imm@@l,%r31,%rn +@end smallexample + +Similarly for the others, except for @code{and} which expands to: +@smallexample +andnot (-1 - large_imm)@@h,%rx,%r31 +andnot (-1 - large_imm)@@l,%r31,%rn +@end smallexample +@end itemize + +@node Syntax of i860 +@section i860 Syntax +@menu +* i860-Chars:: Special Characters +@end menu + +@node i860-Chars +@subsection Special Characters + +@cindex line comment character, i860 +@cindex i860 line comment character +The presence of a @samp{#} appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. + +If a @samp{#} appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (@pxref{Comments}) or a preprocessor +control command (@pxref{Preprocessing}). + +@cindex line separator, i860 +@cindex statement separator, i860 +@cindex i860 line separator +The @samp{;} character can be used to separate statements on the same +line. diff --git a/gas/doc/local.mk b/gas/doc/local.mk index 4185cfe9a3c..fb9c6eb320e 100644 --- a/gas/doc/local.mk +++ b/gas/doc/local.mk @@ -60,6 +60,7 @@ CPU_DOCS = \ %D%/c-h8300.texi \ %D%/c-hppa.texi \ %D%/c-i386.texi \ + %D%/c-i860.texi \ %D%/c-ip2k.texi \ %D%/c-kvx.texi \ %D%/c-lm32.texi \ diff --git a/gas/po/POTFILES.in b/gas/po/POTFILES.in index b78f61370fd..97cf5a86d86 100644 --- a/gas/po/POTFILES.in +++ b/gas/po/POTFILES.in @@ -80,6 +80,8 @@ config/tc-hppa.c config/tc-hppa.h config/tc-i386.c config/tc-i386.h +config/tc-i860.c +config/tc-i860.h config/tc-ia64.c config/tc-ia64.h config/tc-ip2k.c diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index 8ae48b2aeb6..fb1ad6ce3ab 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -442,7 +442,8 @@ if { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } { run_dump_test quad-div {{as --divide}} run_dump_test quad-div2 {{as --divide}} run_dump_test octa-div {{as --divide}} -} elseif { ![istarget "mcore-*-*"] +} elseif { ![istarget "i860-*-*"] + && ![istarget "mcore-*-*"] && ![istarget "mmix-*-*"] && ![istarget "pdp11-*-*"] && ![istarget "pj*-*-*"] } { diff --git a/gas/testsuite/gas/i860/README.i860 b/gas/testsuite/gas/i860/README.i860 new file mode 100644 index 00000000000..47feaa416c8 --- /dev/null +++ b/gas/testsuite/gas/i860/README.i860 @@ -0,0 +1,39 @@ + +Testsuite for the i860 version of the GNU assembler +--------------------------------------------------- + +This is a simple testsuite for the i860 assembler. It currently +consists mostly of testcases for checking that every instruction is +parsed correctly and that correct object code is generated (these +are called "blah.s"). The files called "blah-err.s" test for error +conditions. + +The suite includes testcases for the base i860XR instruction set as well +as the enhanced i860XP instructions and control registers. + +The expected results files were generated using the UNIX System V/i860 +Release 4 vendor assembler (/usr/ccs/bin/as -V reports version +"Standard C Development Environment (SCDE) 5.0 12/08/89"). This +way GAS/i860 is tested against a known good assembler. + +TODO: + - Relocation testing is basically non-existent. + - pst.d (pixel store) is the only instruction with no testcase. + - Some pseudo instructions need testcases (mov, all pfmov, etc.). + - More tests for dual instruction mode: check that dual mode has a + proper pair (FLOP/core) of instructions, and other error conditions. + - Most current testcases use the default AT&T/SVR4 syntax; a few simple + tests of the Intel syntax should be added to prevent bitrot (including + relocatable expression syntax, etc). Test file dual03.s uses Intel + syntax lightly (i.e., register names without '%' prefix). + +Contact me (Jason Eckhardt, jle@rice.edu) if you'd like to help. + +Known testsuite failures: + - none. + +Copyright (C) 2012-2018 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/gas/testsuite/gas/i860/bitwise.d b/gas/testsuite/gas/i860/bitwise.d new file mode 100644 index 00000000000..59954a48769 --- /dev/null +++ b/gas/testsuite/gas/i860/bitwise.d @@ -0,0 +1,141 @@ +#as: +#objdump: -dr +#name: i860 bitwise + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 22 c0 and %r0,%r1,%sp + 4: 00 18 85 c0 and %fp,%r4,%r5 + 8: 00 30 e8 c0 and %r6,%r7,%r8 + c: 00 48 4b c1 and %r9,%r10,%r11 + 10: 00 60 ae c1 and %r12,%r13,%r14 + 14: 00 78 11 c2 and %r15,%r16,%r17 + 18: 00 90 74 c2 and %r18,%r19,%r20 + 1c: 00 a8 d7 c2 and %r21,%r22,%r23 + 20: 00 c0 3a c3 and %r24,%r25,%r26 + 24: 00 d8 9d c3 and %r27,%r28,%r29 + 28: 00 f0 e0 c3 and %r30,%r31,%r0 + 2c: 00 00 22 d0 andnot %r0,%r1,%sp + 30: 00 18 85 d0 andnot %fp,%r4,%r5 + 34: 00 30 e8 d0 andnot %r6,%r7,%r8 + 38: 00 48 4b d1 andnot %r9,%r10,%r11 + 3c: 00 60 ae d1 andnot %r12,%r13,%r14 + 40: 00 78 11 d2 andnot %r15,%r16,%r17 + 44: 00 90 74 d2 andnot %r18,%r19,%r20 + 48: 00 a8 d7 d2 andnot %r21,%r22,%r23 + 4c: 00 c0 3a d3 andnot %r24,%r25,%r26 + 50: 00 d8 9d d3 andnot %r27,%r28,%r29 + 54: 00 f0 e0 d3 andnot %r30,%r31,%r0 + 58: 00 00 22 e0 or %r0,%r1,%sp + 5c: 00 18 85 e0 or %fp,%r4,%r5 + 60: 00 30 e8 e0 or %r6,%r7,%r8 + 64: 00 48 4b e1 or %r9,%r10,%r11 + 68: 00 60 ae e1 or %r12,%r13,%r14 + 6c: 00 78 11 e2 or %r15,%r16,%r17 + 70: 00 90 74 e2 or %r18,%r19,%r20 + 74: 00 a8 d7 e2 or %r21,%r22,%r23 + 78: 00 c0 3a e3 or %r24,%r25,%r26 + 7c: 00 d8 9d e3 or %r27,%r28,%r29 + 80: 00 f0 e0 e3 or %r30,%r31,%r0 + 84: 00 00 22 f0 xor %r0,%r1,%sp + 88: 00 18 85 f0 xor %fp,%r4,%r5 + 8c: 00 30 e8 f0 xor %r6,%r7,%r8 + 90: 00 48 4b f1 xor %r9,%r10,%r11 + 94: 00 60 ae f1 xor %r12,%r13,%r14 + 98: 00 78 11 f2 xor %r15,%r16,%r17 + 9c: 00 90 74 f2 xor %r18,%r19,%r20 + a0: 00 a8 d7 f2 xor %r21,%r22,%r23 + a4: 00 c0 3a f3 xor %r24,%r25,%r26 + a8: 00 d8 9d f3 xor %r27,%r28,%r29 + ac: 00 f0 e0 f3 xor %r30,%r31,%r0 + b0: 00 00 22 c4 and 0x0000,%r1,%sp + b4: 00 20 85 c4 and 0x2000,%r4,%r5 + b8: f5 13 e8 c4 and 0x13f5,%r7,%r8 + bc: 00 80 4b c5 and 0x8000,%r10,%r11 + c0: e8 fd ae c5 and 0xfde8,%r13,%r14 + c4: ff ff 11 c6 and 0xffff,%r16,%r17 + c8: ff ff 74 c6 and 0xffff,%r19,%r20 + cc: cd ab d7 c6 and 0xabcd,%r22,%r23 + d0: 34 12 3a c7 and 0x1234,%r25,%r26 + d4: 00 00 9d c7 and 0x0000,%r28,%r29 + d8: 03 00 e0 c7 and 0x0003,%r31,%r0 + dc: 01 00 22 cc andh 0x0001,%r1,%sp + e0: 01 20 85 cc andh 0x2001,%r4,%r5 + e4: f6 13 e8 cc andh 0x13f6,%r7,%r8 + e8: 01 80 4b cd andh 0x8001,%r10,%r11 + ec: e9 fd ae cd andh 0xfde9,%r13,%r14 + f0: ff ff 11 ce andh 0xffff,%r16,%r17 + f4: ff ff 74 ce andh 0xffff,%r19,%r20 + f8: cd ab d7 ce andh 0xabcd,%r22,%r23 + fc: 34 12 3a cf andh 0x1234,%r25,%r26 + 100: 00 00 9d cf andh 0x0000,%r28,%r29 + 104: 03 00 e0 cf andh 0x0003,%r31,%r0 + 108: 00 00 22 d4 andnot 0x0000,%r1,%sp + 10c: 00 20 85 d4 andnot 0x2000,%r4,%r5 + 110: f5 13 e8 d4 andnot 0x13f5,%r7,%r8 + 114: 00 80 4b d5 andnot 0x8000,%r10,%r11 + 118: e8 fd ae d5 andnot 0xfde8,%r13,%r14 + 11c: ff ff 11 d6 andnot 0xffff,%r16,%r17 + 120: ff ff 74 d6 andnot 0xffff,%r19,%r20 + 124: cd ab d7 d6 andnot 0xabcd,%r22,%r23 + 128: 34 12 3a d7 andnot 0x1234,%r25,%r26 + 12c: 00 00 9d d7 andnot 0x0000,%r28,%r29 + 130: 03 00 e0 d7 andnot 0x0003,%r31,%r0 + 134: 01 00 22 dc andnoth 0x0001,%r1,%sp + 138: 01 20 85 dc andnoth 0x2001,%r4,%r5 + 13c: f6 13 e8 dc andnoth 0x13f6,%r7,%r8 + 140: 01 80 4b dd andnoth 0x8001,%r10,%r11 + 144: e9 fd ae dd andnoth 0xfde9,%r13,%r14 + 148: ff ff 11 de andnoth 0xffff,%r16,%r17 + 14c: ff ff 74 de andnoth 0xffff,%r19,%r20 + 150: cd ab d7 de andnoth 0xabcd,%r22,%r23 + 154: 34 12 3a df andnoth 0x1234,%r25,%r26 + 158: 00 00 9d df andnoth 0x0000,%r28,%r29 + 15c: 03 00 e0 df andnoth 0x0003,%r31,%r0 + 160: 00 00 22 e4 or 0x0000,%r1,%sp + 164: 01 00 85 e4 or 0x0001,%r4,%r5 + 168: 02 00 e8 e4 or 0x0002,%r7,%r8 + 16c: 03 00 4b e5 or 0x0003,%r10,%r11 + 170: e8 fd ae e5 or 0xfde8,%r13,%r14 + 174: ff ff 11 e6 or 0xffff,%r16,%r17 + 178: ff ff 74 e6 or 0xffff,%r19,%r20 + 17c: cd ab d7 e6 or 0xabcd,%r22,%r23 + 180: 34 12 3a e7 or 0x1234,%r25,%r26 + 184: 00 00 9d e7 or 0x0000,%r28,%r29 + 188: 03 00 e0 e7 or 0x0003,%r31,%r0 + 18c: 00 00 22 ec orh 0x0000,%r1,%sp + 190: 01 00 85 ec orh 0x0001,%r4,%r5 + 194: 02 00 e8 ec orh 0x0002,%r7,%r8 + 198: 03 00 4b ed orh 0x0003,%r10,%r11 + 19c: e8 fd ae ed orh 0xfde8,%r13,%r14 + 1a0: ff ff 11 ee orh 0xffff,%r16,%r17 + 1a4: ff ff 74 ee orh 0xffff,%r19,%r20 + 1a8: cd ab d7 ee orh 0xabcd,%r22,%r23 + 1ac: 34 12 3a ef orh 0x1234,%r25,%r26 + 1b0: 00 00 9d ef orh 0x0000,%r28,%r29 + 1b4: 03 00 e0 ef orh 0x0003,%r31,%r0 + 1b8: 00 00 22 f4 xor 0x0000,%r1,%sp + 1bc: 01 00 85 f4 xor 0x0001,%r4,%r5 + 1c0: 02 00 e8 f4 xor 0x0002,%r7,%r8 + 1c4: 03 00 4b f5 xor 0x0003,%r10,%r11 + 1c8: e8 fd ae f5 xor 0xfde8,%r13,%r14 + 1cc: ff ff 11 f6 xor 0xffff,%r16,%r17 + 1d0: ff ff 74 f6 xor 0xffff,%r19,%r20 + 1d4: cd ab d7 f6 xor 0xabcd,%r22,%r23 + 1d8: 34 12 3a f7 xor 0x1234,%r25,%r26 + 1dc: 00 00 9d f7 xor 0x0000,%r28,%r29 + 1e0: 03 00 e0 f7 xor 0x0003,%r31,%r0 + 1e4: 00 00 22 fc xorh 0x0000,%r1,%sp + 1e8: 01 00 85 fc xorh 0x0001,%r4,%r5 + 1ec: 02 00 e8 fc xorh 0x0002,%r7,%r8 + 1f0: 03 00 4b fd xorh 0x0003,%r10,%r11 + 1f4: e8 fd ae fd xorh 0xfde8,%r13,%r14 + 1f8: ff ff 11 fe xorh 0xffff,%r16,%r17 + 1fc: ff ff 74 fe xorh 0xffff,%r19,%r20 + 200: cd ab d7 fe xorh 0xabcd,%r22,%r23 + 204: 34 12 3a ff xorh 0x1234,%r25,%r26 + 208: 00 00 9d ff xorh 0x0000,%r28,%r29 + 20c: 03 00 e0 ff xorh 0x0003,%r31,%r0 diff --git a/gas/testsuite/gas/i860/bitwise.s b/gas/testsuite/gas/i860/bitwise.s new file mode 100644 index 00000000000..531c7877558 --- /dev/null +++ b/gas/testsuite/gas/i860/bitwise.s @@ -0,0 +1,150 @@ +# and, andh, andnot, andnoth, or, orh, xor, xorh + + .text + + # Register forms (high variants do not have register forms). + and %r0,%r1,%r2 + and %r3,%r4,%r5 + and %r6,%r7,%r8 + and %r9,%r10,%r11 + and %r12,%r13,%r14 + and %r15,%r16,%r17 + and %r18,%r19,%r20 + and %r21,%r22,%r23 + and %r24,%r25,%r26 + and %r27,%r28,%r29 + and %r30,%r31,%r0 + + andnot %r0,%r1,%r2 + andnot %r3,%r4,%r5 + andnot %r6,%r7,%r8 + andnot %r9,%r10,%r11 + andnot %r12,%r13,%r14 + andnot %r15,%r16,%r17 + andnot %r18,%r19,%r20 + andnot %r21,%r22,%r23 + andnot %r24,%r25,%r26 + andnot %r27,%r28,%r29 + andnot %r30,%r31,%r0 + + or %r0,%r1,%r2 + or %r3,%r4,%r5 + or %r6,%r7,%r8 + or %r9,%r10,%r11 + or %r12,%r13,%r14 + or %r15,%r16,%r17 + or %r18,%r19,%r20 + or %r21,%r22,%r23 + or %r24,%r25,%r26 + or %r27,%r28,%r29 + or %r30,%r31,%r0 + + xor %r0,%r1,%r2 + xor %r3,%r4,%r5 + xor %r6,%r7,%r8 + xor %r9,%r10,%r11 + xor %r12,%r13,%r14 + xor %r15,%r16,%r17 + xor %r18,%r19,%r20 + xor %r21,%r22,%r23 + xor %r24,%r25,%r26 + xor %r27,%r28,%r29 + xor %r30,%r31,%r0 + + # Immediate forms (all) + and 0,%r1,%r2 + and 8192,%r4,%r5 + and 5109,%r7,%r8 + and 32768,%r10,%r11 + and 65000,%r13,%r14 + and 65535,%r16,%r17 + and 0xffff,%r19,%r20 + and 0xabcd,%r22,%r23 + and 0x1234,%r25,%r26 + and 0x0,%r28,%r29 + and 0x3,%r31,%r0 + + andh 1,%r1,%r2 + andh 8193,%r4,%r5 + andh 5110,%r7,%r8 + andh 32769,%r10,%r11 + andh 65001,%r13,%r14 + andh 65535,%r16,%r17 + andh 0xffff,%r19,%r20 + andh 0xabcd,%r22,%r23 + andh 0x1234,%r25,%r26 + andh 0x0,%r28,%r29 + andh 0x3,%r31,%r0 + + andnot 0,%r1,%r2 + andnot 8192,%r4,%r5 + andnot 5109,%r7,%r8 + andnot 32768,%r10,%r11 + andnot 65000,%r13,%r14 + andnot 65535,%r16,%r17 + andnot 0xffff,%r19,%r20 + andnot 0xabcd,%r22,%r23 + andnot 0x1234,%r25,%r26 + andnot 0x0,%r28,%r29 + andnot 0x3,%r31,%r0 + + andnoth 1,%r1,%r2 + andnoth 8193,%r4,%r5 + andnoth 5110,%r7,%r8 + andnoth 32769,%r10,%r11 + andnoth 65001,%r13,%r14 + andnoth 65535,%r16,%r17 + andnoth 0xffff,%r19,%r20 + andnoth 0xabcd,%r22,%r23 + andnoth 0x1234,%r25,%r26 + andnoth 0x0,%r28,%r29 + andnoth 0x3,%r31,%r0 + + or 0,%r1,%r2 + or 1,%r4,%r5 + or 2,%r7,%r8 + or 3,%r10,%r11 + or 65000,%r13,%r14 + or 65535,%r16,%r17 + or 0xffff,%r19,%r20 + or 0xabcd,%r22,%r23 + or 0x1234,%r25,%r26 + or 0x0,%r28,%r29 + or 0x3,%r31,%r0 + + orh 0,%r1,%r2 + orh 1,%r4,%r5 + orh 2,%r7,%r8 + orh 3,%r10,%r11 + orh 65000,%r13,%r14 + orh 65535,%r16,%r17 + orh 0xffff,%r19,%r20 + orh 0xabcd,%r22,%r23 + orh 0x1234,%r25,%r26 + orh 0x0,%r28,%r29 + orh 0x3,%r31,%r0 + + xor 0,%r1,%r2 + xor 1,%r4,%r5 + xor 2,%r7,%r8 + xor 3,%r10,%r11 + xor 65000,%r13,%r14 + xor 65535,%r16,%r17 + xor 0xffff,%r19,%r20 + xor 0xabcd,%r22,%r23 + xor 0x1234,%r25,%r26 + xor 0x0,%r28,%r29 + xor 0x3,%r31,%r0 + + xorh 0,%r1,%r2 + xorh 1,%r4,%r5 + xorh 2,%r7,%r8 + xorh 3,%r10,%r11 + xorh 65000,%r13,%r14 + xorh 65535,%r16,%r17 + xorh 0xffff,%r19,%r20 + xorh 0xabcd,%r22,%r23 + xorh 0x1234,%r25,%r26 + xorh 0x0,%r28,%r29 + xorh 0x3,%r31,%r0 + diff --git a/gas/testsuite/gas/i860/branch.d b/gas/testsuite/gas/i860/branch.d new file mode 100644 index 00000000000..eba23d6dafa --- /dev/null +++ b/gas/testsuite/gas/i860/branch.d @@ -0,0 +1,81 @@ +#as: +#objdump: -dr +#name: i860 branch + +.*: +file format .* + +Disassembly of section .text: + +00000000 <.text>: + 0: 3d 00 20 b4 bla %r0,%r1,0x000000f8 // 0xf8 + 4: 00 00 00 a0 shl %r0,%r0,%r0 + 8: 3d 28 e0 b7 bla %r5,%r31,0x00000100 // 0x100 + c: 00 00 00 a0 shl %r0,%r0,%r0 + 10: 39 b8 00 b6 bla %r23,%r16,0x000000f8 // 0xf8 + 14: 00 00 00 a0 shl %r0,%r0,%r0 + 18: 39 20 60 b6 bla %r4,%r19,0x00000100 // 0x100 + 1c: 00 00 00 a0 shl %r0,%r0,%r0 + 20: 00 00 00 40 bri %r0 + 24: 00 00 00 a0 shl %r0,%r0,%r0 + 28: 00 08 00 40 bri %r1 + 2c: 00 00 00 a0 shl %r0,%r0,%r0 + 30: 00 f8 00 40 bri %r31 + 34: 00 00 00 a0 shl %r0,%r0,%r0 + 38: 00 08 00 40 bri %r1 + 3c: 00 00 00 a0 shl %r0,%r0,%r0 + 40: 00 60 00 40 bri %r12 + 44: 00 00 00 a0 shl %r0,%r0,%r0 + 48: 00 98 00 40 bri %r19 + 4c: 00 00 00 a0 shl %r0,%r0,%r0 + 50: 02 00 00 4c calli %r0 + 54: 00 00 00 a0 shl %r0,%r0,%r0 + 58: 02 08 00 4c calli %r1 + 5c: 00 00 00 a0 shl %r0,%r0,%r0 + 60: 02 f8 00 4c calli %r31 + 64: 00 00 00 a0 shl %r0,%r0,%r0 + 68: 02 28 00 4c calli %r5 + 6c: 00 00 00 a0 shl %r0,%r0,%r0 + 70: 02 b0 00 4c calli %r22 + 74: 00 00 00 a0 shl %r0,%r0,%r0 + 78: 02 48 00 4c calli %r9 + 7c: 00 00 00 a0 shl %r0,%r0,%r0 + 80: 1d 00 00 68 br 0x000000f8 // 0xf8 + 84: 00 00 00 a0 shl %r0,%r0,%r0 + 88: 1d 00 00 68 br 0x00000100 // 0x100 + 8c: 00 00 00 a0 shl %r0,%r0,%r0 + 90: 00 00 00 68 br 0x00000094 // 0x94 + 90: R_860_PC26 some_fake_extern + 94: 00 00 00 a0 shl %r0,%r0,%r0 + 98: 17 00 00 6c call 0x000000f8 // 0xf8 + 9c: 00 00 00 a0 shl %r0,%r0,%r0 + a0: 17 00 00 6c call 0x00000100 // 0x100 + a4: 00 00 00 a0 shl %r0,%r0,%r0 + a8: 00 00 00 6c call 0x000000ac // 0xac + a8: R_860_PC26 some_fake_extern + ac: 00 00 00 a0 shl %r0,%r0,%r0 + b0: 02 00 00 70 bc 0x000000bc // 0xbc + b4: 10 00 00 70 bc 0x000000f8 // 0xf8 + b8: 00 00 00 70 bc 0x000000bc // 0xbc + b8: R_860_PC26 some_fake_extern + bc: ff ff ff 77 bc.t 0x000000bc // 0xbc + c0: 00 00 00 a0 shl %r0,%r0,%r0 + c4: 0c 00 00 74 bc.t 0x000000f8 // 0xf8 + c8: 00 00 00 a0 shl %r0,%r0,%r0 + cc: 00 00 00 74 bc.t 0x000000d0 // 0xd0 + cc: R_860_PC26 some_fake_extern + d0: 00 00 00 a0 shl %r0,%r0,%r0 + d4: 02 00 00 78 bnc 0x000000e0 // 0xe0 + d8: 07 00 00 78 bnc 0x000000f8 // 0xf8 + dc: 00 00 00 78 bnc 0x000000e0 // 0xe0 + dc: R_860_PC26 some_fake_extern + e0: ff ff ff 7f bnc.t 0x000000e0 // 0xe0 + e4: 00 00 00 a0 shl %r0,%r0,%r0 + e8: 03 00 00 7c bnc.t 0x000000f8 // 0xf8 + ec: 00 00 00 a0 shl %r0,%r0,%r0 + f0: 00 00 00 7c bnc.t 0x000000f4 // 0xf4 + f0: R_860_PC26 some_fake_extern + f4: 00 00 00 a0 shl %r0,%r0,%r0 + f8: 00 00 00 a0 shl %r0,%r0,%r0 + fc: 00 00 00 a0 shl %r0,%r0,%r0 + 100: 00 00 00 a0 shl %r0,%r0,%r0 + 104: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/branch.s b/gas/testsuite/gas/i860/branch.s new file mode 100644 index 00000000000..3df2758a640 --- /dev/null +++ b/gas/testsuite/gas/i860/branch.s @@ -0,0 +1,85 @@ +# Branches and calls + + .text + + bla %r0,%r1,.Lsome_label1 + nop + bla %r5,%r31,.Lsome_label2 + nop + bla %r23,%r16,.Lsome_label1 + nop + bla %r4,%r19,.Lsome_label2 + nop + + bri %r0 + nop + bri %r1 + nop + bri %r31 + nop + bri %r1 + nop + bri %r12 + nop + bri %r19 + nop + + calli %r0 + nop + calli %r1 + nop + calli %r31 + nop + calli %r5 + nop + calli %r22 + nop + calli %r9 + nop + + br .Lsome_label1 + nop + br .Lsome_label2 + nop + br some_fake_extern + nop + + call .Lcall_me_now + nop + call .Lcall_me_anytime + nop + call some_fake_extern + nop + + bc .+12 + bc .Lsome_label1 + bc some_fake_extern + + bc.t .+0 + nop + bc.t .Lsome_label1 + nop + bc.t some_fake_extern + nop + + bnc .+12 + bnc .Lsome_label1 + bnc some_fake_extern + + bnc.t .+0 + nop + bnc.t .Lsome_label1 + nop + bnc.t some_fake_extern + nop + + +.Lsome_label1: +.Lcall_me_now: + nop + nop +.Lsome_label2: +.Lcall_me_anytime: + nop + nop + diff --git a/gas/testsuite/gas/i860/bte.d b/gas/testsuite/gas/i860/bte.d new file mode 100644 index 00000000000..a8f4404f1fa --- /dev/null +++ b/gas/testsuite/gas/i860/bte.d @@ -0,0 +1,62 @@ +#as: +#objdump: -dr +#name: i860 bte/btne + +.*: +file format .* + +Disassembly of section \.text: + +00000000 : + 0: 2d 00 e0 57 btne 0,%r31,0x000000b8 // b8 + 4: 2c 08 a0 57 btne 1,%r29,0x000000b8 // b8 + 8: 2b 10 60 57 btne 2,%r27,0x000000b8 // b8 + c: 2a 18 20 57 btne 3,%r25,0x000000b8 // b8 + 10: 29 50 e0 56 btne 10,%r23,0x000000b8 // b8 + 14: 28 58 a0 56 btne 11,%r21,0x000000b8 // b8 + 18: 27 60 60 56 btne 12,%r19,0x000000b8 // b8 + 1c: 26 e8 20 56 btne 29,%r17,0x000000b8 // b8 + 20: 25 f0 00 56 btne 30,%r16,0x000000b8 // b8 + 24: 24 f8 00 55 btne 31,%r8,0x000000b8 // b8 + 28: 00 78 00 54 btne 15,%r0,0x0000002c // 2c + 28: R_860_PC16 some_fake_extern + 2c: 22 00 e0 5f bte 0,%r31,0x000000b8 // b8 + 30: 21 08 a0 5f bte 1,%r29,0x000000b8 // b8 + 34: 20 10 60 5f bte 2,%r27,0x000000b8 // b8 + 38: 1f 18 20 5f bte 3,%r25,0x000000b8 // b8 + 3c: 1e 50 e0 5e bte 10,%r23,0x000000b8 // b8 + 40: 1d 58 a0 5e bte 11,%r21,0x000000b8 // b8 + 44: 1c 60 60 5e bte 12,%r19,0x000000b8 // b8 + 48: 1b e8 20 5e bte 29,%r17,0x000000b8 // b8 + 4c: 1a f0 00 5e bte 30,%r16,0x000000b8 // b8 + 50: 19 f8 00 5d bte 31,%r8,0x000000b8 // b8 + 54: 00 78 00 5c bte 15,%r0,0x00000058 // 58 + 54: R_860_PC16 some_fake_extern + 58: 17 00 e0 53 btne %r0,%r31,0x000000b8 // b8 + 5c: 16 08 a0 53 btne %r1,%r29,0x000000b8 // b8 + 60: 15 10 60 53 btne %sp,%r27,0x000000b8 // b8 + 64: 14 18 20 53 btne %fp,%r25,0x000000b8 // b8 + 68: 13 50 e0 52 btne %r10,%r23,0x000000b8 // b8 + 6c: 12 58 a0 52 btne %r11,%r21,0x000000b8 // b8 + 70: 11 60 60 52 btne %r12,%r19,0x000000b8 // b8 + 74: 10 e8 20 52 btne %r29,%r17,0x000000b8 // b8 + 78: 0f f0 00 52 btne %r30,%r16,0x000000b8 // b8 + 7c: 0e f8 00 51 btne %r31,%r8,0x000000b8 // b8 + 80: 00 78 00 50 btne %r15,%r0,0x00000084 // 84 + 80: R_860_PC16 some_fake_extern + 84: 0c 00 e0 5b bte %r0,%r31,0x000000b8 // b8 + 88: 0b 08 a0 5b bte %r1,%r29,0x000000b8 // b8 + 8c: 0a 10 60 5b bte %sp,%r27,0x000000b8 // b8 + 90: 09 18 20 5b bte %fp,%r25,0x000000b8 // b8 + 94: 08 50 e0 5a bte %r10,%r23,0x000000b8 // b8 + 98: 07 58 a0 5a bte %r11,%r21,0x000000b8 // b8 + 9c: 06 60 60 5a bte %r12,%r19,0x000000b8 // b8 + a0: 05 e8 20 5a bte %r29,%r17,0x000000b8 // b8 + a4: 04 f0 00 5a bte %r30,%r16,0x000000b8 // b8 + a8: 03 f8 00 59 bte %r31,%r8,0x000000b8 // b8 + ac: 00 78 00 58 bte %r15,%r0,0x000000b0 // b0 + ac: R_860_PC16 some_fake_extern + b0: 00 00 00 a0 shl %r0,%r0,%r0 + b4: 00 00 00 a0 shl %r0,%r0,%r0 + +000000b8 : + b8: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/bte.s b/gas/testsuite/gas/i860/bte.s new file mode 100644 index 00000000000..cc6e57693f5 --- /dev/null +++ b/gas/testsuite/gas/i860/bte.s @@ -0,0 +1,55 @@ +# bte, btne + .text + + btne 0,%r31,some_label + btne 1,%r29,some_label + btne 2,%r27,some_label + btne 3,%r25,some_label + btne 10,%r23,some_label + btne 11,%r21,some_label + btne 12,%r19,some_label + btne 29,%r17,some_label + btne 30,%r16,some_label + btne 31,%r8,some_label + btne 15,%r0,some_fake_extern + + bte 0,%r31,some_label + bte 1,%r29,some_label + bte 2,%r27,some_label + bte 3,%r25,some_label + bte 10,%r23,some_label + bte 11,%r21,some_label + bte 12,%r19,some_label + bte 29,%r17,some_label + bte 30,%r16,some_label + bte 31,%r8,some_label + bte 15,%r0,some_fake_extern + + btne %r0,%r31,some_label + btne %r1,%r29,some_label + btne %r2,%r27,some_label + btne %r3,%r25,some_label + btne %r10,%r23,some_label + btne %r11,%r21,some_label + btne %r12,%r19,some_label + btne %r29,%r17,some_label + btne %r30,%r16,some_label + btne %r31,%r8,some_label + btne %r15,%r0,some_fake_extern + + bte %r0,%r31,some_label + bte %r1,%r29,some_label + bte %r2,%r27,some_label + bte %r3,%r25,some_label + bte %r10,%r23,some_label + bte %r11,%r21,some_label + bte %r12,%r19,some_label + bte %r29,%r17,some_label + bte %r30,%r16,some_label + bte %r31,%r8,some_label + bte %r15,%r0,some_fake_extern + + nop + nop +some_label: + nop diff --git a/gas/testsuite/gas/i860/dir-align01.d b/gas/testsuite/gas/i860/dir-align01.d new file mode 100644 index 00000000000..bc4f677074a --- /dev/null +++ b/gas/testsuite/gas/i860/dir-align01.d @@ -0,0 +1,17 @@ +#as: +#objdump: -d +#name: i860 dir-align01 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 20 a6 90 adds %r4,%r5,%r6 + 4: 00 00 00 a0 shl %r0,%r0,%r0 + 8: 00 00 00 a0 shl %r0,%r0,%r0 + c: 00 00 00 a0 shl %r0,%r0,%r0 + 10: 00 50 6c 91 adds %r10,%r11,%r12 + 14: a1 b1 1a 4b fmlow.dd %f22,%f24,%f26 + 18: 30 74 f0 49 pfadd.ss %f14,%f15,%f16 + 1c: b0 8c 54 4a pfadd.sd %f17,%f18,%f20 diff --git a/gas/testsuite/gas/i860/dir-align01.s b/gas/testsuite/gas/i860/dir-align01.s new file mode 100644 index 00000000000..595eb3fcff1 --- /dev/null +++ b/gas/testsuite/gas/i860/dir-align01.s @@ -0,0 +1,11 @@ +# Test that .text section alignments use nops (0xA0000000) to fill +# rather than 0. + .text + adds %r4,%r5,%r6 + .align 16 + adds %r10,%r11,%r12 + fmlow.dd %f22,%f24,%f26 + pfadd.ss %f14,%f15,%f16 + pfadd.sd %f17,%f18,%f20 + + diff --git a/gas/testsuite/gas/i860/dir-intel01.d b/gas/testsuite/gas/i860/dir-intel01.d new file mode 100644 index 00000000000..0951bf36027 --- /dev/null +++ b/gas/testsuite/gas/i860/dir-intel01.d @@ -0,0 +1,19 @@ +#as: -mintel-syntax +#objdump: -d +#name: i860 dir-intel01 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 a0 shl %r0,%r0,%r0 + 4: 00 00 00 a0 shl %r0,%r0,%r0 + 8: 30 02 22 48 d.fadd.ss %f0,%f1,%f2 + c: 00 00 00 a0 shl %r0,%r0,%r0 + 10: b0 12 64 48 d.fadd.sd %f2,%f3,%f4 + 14: 00 00 00 a0 shl %r0,%r0,%r0 + 18: b0 33 0a 49 d.fadd.dd %f6,%f8,%f10 + 1c: 00 00 00 a0 shl %r0,%r0,%r0 + 20: 00 00 00 a0 shl %r0,%r0,%r0 + 24: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/dir-intel01.s b/gas/testsuite/gas/i860/dir-intel01.s new file mode 100644 index 00000000000..21aa685ed2e --- /dev/null +++ b/gas/testsuite/gas/i860/dir-intel01.s @@ -0,0 +1,19 @@ +// Intel assembler directives: +// Test that the .dual and .enddual directives are recognized and +// function (i.e., that the dual bits are set properly). + + .text + + nop + nop + .dual + fadd.ss f0,f1,f2 + nop + fadd.sd f2,f3,f4 + nop + fadd.dd f6,f8,f10 + nop + .enddual + nop + nop + diff --git a/gas/testsuite/gas/i860/dir-intel02.d b/gas/testsuite/gas/i860/dir-intel02.d new file mode 100644 index 00000000000..f053967a5e6 --- /dev/null +++ b/gas/testsuite/gas/i860/dir-intel02.d @@ -0,0 +1,15 @@ +#as: -mintel-syntax +#objdump: -d +#name: i860 dir-intel02 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 34 12 1f ec orh 0x1234,%r0,%r31 + 4: 78 56 f8 e7 or 0x5678,%r31,%r24 + 8: 00 c0 28 91 adds %r24,%r9,%r8 + c: f0 f0 05 ec orh 0xf0f0,%r0,%r5 + 10: 5a 5a b8 e4 or 0x5a5a,%r5,%r24 + 14: 00 c0 28 91 adds %r24,%r9,%r8 diff --git a/gas/testsuite/gas/i860/dir-intel02.s b/gas/testsuite/gas/i860/dir-intel02.s new file mode 100644 index 00000000000..a1a161371f1 --- /dev/null +++ b/gas/testsuite/gas/i860/dir-intel02.s @@ -0,0 +1,13 @@ +// Intel assembler directives: +// Test that the .atmp directive is recognized and functions. + + .text + + .atmp r31 + or 0x12345678,r0,r24 + adds r24,r9,r8 + + .atmp r5 + or 0xf0f05a5a,r0,r24 + adds r24,r9,r8 + diff --git a/gas/testsuite/gas/i860/dir-intel03-err.l b/gas/testsuite/gas/i860/dir-intel03-err.l new file mode 100644 index 00000000000..b8261282bf7 --- /dev/null +++ b/gas/testsuite/gas/i860/dir-intel03-err.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*:8: Error: Directive .atmp available only with -mintel-syntax option +.*:8: Error: junk at end of line, first unrecognized character is `r' +.*:10: Error: Directive .dual available only with -mintel-syntax option +.*:13: Error: Directive .enddual available only with -mintel-syntax option diff --git a/gas/testsuite/gas/i860/dir-intel03-err.s b/gas/testsuite/gas/i860/dir-intel03-err.s new file mode 100644 index 00000000000..b8b07906215 --- /dev/null +++ b/gas/testsuite/gas/i860/dir-intel03-err.s @@ -0,0 +1,14 @@ +# Intel assembler directives: +# The .dual, .enddual, and .atmp directives are valid only +# in Intel syntax mode. Check that we issue an error if in +# AT&T/SVR4 mode. + + .text + + .atmp r31 + + .dual + fsub.ss %f22,%f21,%f13 + nop + .enddual + diff --git a/gas/testsuite/gas/i860/dual-frag.s b/gas/testsuite/gas/i860/dual-frag.s new file mode 100644 index 00000000000..4b40a71ed91 --- /dev/null +++ b/gas/testsuite/gas/i860/dual-frag.s @@ -0,0 +1,10 @@ +# Valid dual mode code longer than a frag: the check of the 8 byte alignment must +# not depend on where a new frag starts. + .text + .align 8 + .rept 20000 + d.fnop + nop + .endr + fnop + nop diff --git a/gas/testsuite/gas/i860/dual01.d b/gas/testsuite/gas/i860/dual01.d new file mode 100644 index 00000000000..ee182e0af71 --- /dev/null +++ b/gas/testsuite/gas/i860/dual01.d @@ -0,0 +1,21 @@ +#as: +#objdump: -d +#name: i860 dual01 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 a0 shl %r0,%r0,%r0 + 4: 00 00 00 a0 shl %r0,%r0,%r0 + 8: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12 + c: 00 28 c6 90 adds %r5,%r6,%r6 + 10: b0 47 4c 49 d.pfadd.dd %f8,%f10,%f12 + 14: 10 00 58 25 fld.d 16\(%r10\),%f24 + 18: 00 02 00 b0 d.shrd %r0,%r0,%r0 + 1c: 08 00 48 25 fld.d 8\(%r10\),%f8 + 20: 00 02 00 b0 d.shrd %r0,%r0,%r0 + 24: 00 00 50 25 fld.d 0\(%r10\),%f16 + 28: 00 00 00 a0 shl %r0,%r0,%r0 + 2c: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/dual01.s b/gas/testsuite/gas/i860/dual01.s new file mode 100644 index 00000000000..e7aa271a79b --- /dev/null +++ b/gas/testsuite/gas/i860/dual01.s @@ -0,0 +1,17 @@ +# Test fnop's dual bit (all other floating point operations have their dual +# bit tested in their individual test files). + + .text + .align 8 + nop + nop + d.pfadd.dd %f8,%f10,%f12 + adds %r5,%r6,%r6 + d.pfadd.dd %f8,%f10,%f12 + fld.d 16(%r10),%f24 + d.fnop + fld.d 8(%r10),%f8 + d.fnop + fld.d 0(%r10),%f16 + nop + nop diff --git a/gas/testsuite/gas/i860/dual02-err.l b/gas/testsuite/gas/i860/dual02-err.l new file mode 100644 index 00000000000..d43d73e46a3 --- /dev/null +++ b/gas/testsuite/gas/i860/dual02-err.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*:7: Error: 'd\.fadd\.ss' must be 8-byte aligned diff --git a/gas/testsuite/gas/i860/dual02-err.s b/gas/testsuite/gas/i860/dual02-err.s new file mode 100644 index 00000000000..05d1835c062 --- /dev/null +++ b/gas/testsuite/gas/i860/dual02-err.s @@ -0,0 +1,9 @@ +# Dual-mode pairs must be aligned on an 8-byte boundary. This tests +# that an error is reported if not properly aligned. + + .text + .align 8 + nop + d.fadd.ss %f3,%f5,%f7 + addu %r4,%r5,%r6 + diff --git a/gas/testsuite/gas/i860/dual03.d b/gas/testsuite/gas/i860/dual03.d new file mode 100644 index 00000000000..30c0130f7c4 --- /dev/null +++ b/gas/testsuite/gas/i860/dual03.d @@ -0,0 +1,53 @@ +#as: -mintel-syntax +#objdump: -d +#name: i860 dual03 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 : + 0: 00 00 14 22 fld.d %r0\(%r16\),%f20 + 4: fe ff 15 94 adds -2,%r0,%r21 + 8: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0 + c: fa ff 31 96 adds -6,%r17,%r17 + 10: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0 + 14: 02 a8 20 b6 bla %r21,%r17,0x00000020 // 20 + 18: 30 06 00 48 d.pfadd.ss %f0,%f0,%f0 + 1c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22 + +00000020 : + 20: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30 + 24: 06 a8 20 b6 bla %r21,%r17,0x00000040 // 40 + 28: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31 + 2c: 09 00 14 26 fld.d 8\(%r16\)\+\+,%f20 + 30: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30 + 34: 0a 00 00 68 br 0x00000060 // 60 + 38: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31 + 3c: 00 00 00 a0 shl %r0,%r0,%r0 + +00000040 : + 40: 30 b6 de 4b d.pfadd.ss %f22,%f30,%f30 + 44: f6 af 3f b6 bla %r21,%r17,0x00000020 // 20 + 48: 30 be ff 4b d.pfadd.ss %f23,%f31,%f31 + 4c: 09 00 16 26 fld.d 8\(%r16\)\+\+,%f22 + 50: 30 a6 de 4b d.pfadd.ss %f20,%f30,%f30 + 54: 00 00 00 a0 shl %r0,%r0,%r0 + 58: 30 ae ff 4b d.pfadd.ss %f21,%f31,%f31 + 5c: 00 00 00 a0 shl %r0,%r0,%r0 + +00000060 : + 60: 30 b4 de 4b pfadd.ss %f22,%f30,%f30 + 64: fc ff 15 94 adds -4,%r0,%r21 + 68: 30 bc ff 4b pfadd.ss %f23,%f31,%f31 + 6c: 02 a8 20 5a bte %r21,%r17,0x00000078 // 78 + 70: 0b 00 14 26 fld.l 8\(%r16\)\+\+,%f20 + 74: 30 a4 de 4b pfadd.ss %f20,%f30,%f30 + +00000078 : + 78: 30 04 1e 48 pfadd.ss %f0,%f0,%f30 + 7c: 30 f4 ff 4b pfadd.ss %f30,%f31,%f31 + 80: 30 04 1e 48 pfadd.ss %f0,%f0,%f30 + 84: 30 04 00 48 pfadd.ss %f0,%f0,%f0 + 88: 30 04 1f 48 pfadd.ss %f0,%f0,%f31 + 8c: 30 f0 f0 4b fadd.ss %f30,%f31,%f16 diff --git a/gas/testsuite/gas/i860/dual03.s b/gas/testsuite/gas/i860/dual03.s new file mode 100644 index 00000000000..96c313429de --- /dev/null +++ b/gas/testsuite/gas/i860/dual03.s @@ -0,0 +1,46 @@ +// A larger dual-mode test, from the programmer's reference manual. +// This uses Intel syntax, as in the manual. + +// Single-precision vector sum + fld.d r0(r16),f20 + mov -2,r21 + d.pfadd.ss f0,f0,f0 + adds -6,r17,r17 + d.pfadd.ss f0,f0,f0 + bla r21,r17,L1 + d.pfadd.ss f0,f0,f0 + fld.d 8(r16)++,f22 +L1: + d.pfadd.ss f20,f30,f30 + bla r21,r17,L2 + d.pfadd.ss f21,f31,f31 + fld.d 8(r16)++,f20 + d.pfadd.ss f20,f30,f30 + br S + d.pfadd.ss f21,f31,f31 + nop +L2: + d.pfadd.ss f22,f30,f30 + bla r21,r17,L1 + d.pfadd.ss f23,f31,f31 + fld.d 8(r16)++,f22 + d.pfadd.ss f20,f30,f30 + nop + d.pfadd.ss f21,f31,f31 + nop +S: + pfadd.ss f22,f30,f30 + mov -4,r21 + pfadd.ss f23,f31,f31 + bte r21,r17,DONE + fld.l 8(r16)++,f20 + pfadd.ss f20,f30,f30 +DONE: + pfadd.ss f0,f0,f30 + pfadd.ss f30,f31,f31 + pfadd.ss f0,f0,f30 + pfadd.ss f0,f0,f0 + pfadd.ss f0,f0,f31 + fadd.ss f30,f31,f16 + + diff --git a/gas/testsuite/gas/i860/fldst01.d b/gas/testsuite/gas/i860/fldst01.d new file mode 100644 index 00000000000..b404d3de337 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst01.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst01 (fld.l) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 02 00 00 24 fld.l 0\(%r0\),%f0 + 4: 7e 00 3f 24 fld.l 124\(%r1\),%f31 + 8: 02 01 5e 24 fld.l 256\(%sp\),%f30 + c: 02 02 7d 24 fld.l 512\(%fp\),%f29 + 10: 02 04 9c 24 fld.l 1024\(%r4\),%f28 + 14: 02 10 bb 24 fld.l 4096\(%r5\),%f27 + 18: 02 20 da 24 fld.l 8192\(%r6\),%f26 + 1c: 02 40 f9 24 fld.l 16384\(%r7\),%f25 + 20: fe 7f f9 24 fld.l 32764\(%r7\),%f25 + 24: 02 80 f7 24 fld.l -32768\(%r7\),%f23 + 28: 02 c0 02 25 fld.l -16384\(%r8\),%f2 + 2c: 02 e0 23 25 fld.l -8192\(%r9\),%f3 + 30: 02 f0 48 25 fld.l -4096\(%r10\),%f8 + 34: 02 fc 69 25 fld.l -1024\(%r11\),%f9 + 38: 06 fe 8c 25 fld.l -508\(%r12\),%f12 + 3c: 0a ff b3 25 fld.l -248\(%r13\),%f19 + 40: fe ff d5 25 fld.l -4\(%r14\),%f21 + 44: 03 00 00 24 fld.l 0\(%r0\)\+\+,%f0 + 48: 7f 00 21 24 fld.l 124\(%r1\)\+\+,%f1 + 4c: 03 01 42 24 fld.l 256\(%sp\)\+\+,%f2 + 50: 03 02 63 24 fld.l 512\(%fp\)\+\+,%f3 + 54: 03 04 84 24 fld.l 1024\(%r4\)\+\+,%f4 + 58: 03 10 a5 24 fld.l 4096\(%r5\)\+\+,%f5 + 5c: 03 20 c6 24 fld.l 8192\(%r6\)\+\+,%f6 + 60: 03 40 e7 24 fld.l 16384\(%r7\)\+\+,%f7 + 64: ff 7f e8 24 fld.l 32764\(%r7\)\+\+,%f8 + 68: 03 80 e9 24 fld.l -32768\(%r7\)\+\+,%f9 + 6c: 03 c0 0a 25 fld.l -16384\(%r8\)\+\+,%f10 + 70: 03 e0 2b 25 fld.l -8192\(%r9\)\+\+,%f11 + 74: 03 f0 4c 25 fld.l -4096\(%r10\)\+\+,%f12 + 78: 03 fc 6d 25 fld.l -1024\(%r11\)\+\+,%f13 + 7c: 07 fe 8e 25 fld.l -508\(%r12\)\+\+,%f14 + 80: 0b ff af 25 fld.l -248\(%r13\)\+\+,%f15 + 84: ff ff d0 25 fld.l -4\(%r14\)\+\+,%f16 + 88: 02 28 00 20 fld.l %r5\(%r0\),%f0 + 8c: 02 30 3f 20 fld.l %r6\(%r1\),%f31 + 90: 02 38 5e 20 fld.l %r7\(%sp\),%f30 + 94: 02 40 7d 20 fld.l %r8\(%fp\),%f29 + 98: 02 48 9c 20 fld.l %r9\(%r4\),%f28 + 9c: 02 00 bb 20 fld.l %r0\(%r5\),%f27 + a0: 02 08 da 20 fld.l %r1\(%r6\),%f26 + a4: 02 60 f9 20 fld.l %r12\(%r7\),%f25 + a8: 02 68 18 21 fld.l %r13\(%r8\),%f24 + ac: 02 70 37 21 fld.l %r14\(%r9\),%f23 + b0: 02 78 56 21 fld.l %r15\(%r10\),%f22 + b4: 02 80 75 21 fld.l %r16\(%r11\),%f21 + b8: 02 88 94 21 fld.l %r17\(%r12\),%f20 + bc: 02 e0 b3 21 fld.l %r28\(%r13\),%f19 + c0: 02 f8 d2 21 fld.l %r31\(%r14\),%f18 + c4: 03 28 00 20 fld.l %r5\(%r0\)\+\+,%f0 + c8: 03 30 21 20 fld.l %r6\(%r1\)\+\+,%f1 + cc: 03 38 42 20 fld.l %r7\(%sp\)\+\+,%f2 + d0: 03 40 63 20 fld.l %r8\(%fp\)\+\+,%f3 + d4: 03 48 84 20 fld.l %r9\(%r4\)\+\+,%f4 + d8: 03 00 a5 20 fld.l %r0\(%r5\)\+\+,%f5 + dc: 03 08 c6 20 fld.l %r1\(%r6\)\+\+,%f6 + e0: 03 60 e7 20 fld.l %r12\(%r7\)\+\+,%f7 + e4: 03 68 08 21 fld.l %r13\(%r8\)\+\+,%f8 + e8: 03 70 29 21 fld.l %r14\(%r9\)\+\+,%f9 + ec: 03 78 4a 21 fld.l %r15\(%r10\)\+\+,%f10 + f0: 03 80 6b 21 fld.l %r16\(%r11\)\+\+,%f11 + f4: 03 88 8c 21 fld.l %r17\(%r12\)\+\+,%f12 + f8: 03 e0 ad 21 fld.l %r28\(%r13\)\+\+,%f13 + fc: 03 f8 ce 21 fld.l %r31\(%r14\)\+\+,%f14 diff --git a/gas/testsuite/gas/i860/fldst01.s b/gas/testsuite/gas/i860/fldst01.s new file mode 100644 index 00000000000..109cba85f77 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst01.s @@ -0,0 +1,75 @@ +# fld.l (no relocations here) + .text + + # Immediate form, no auto-increment. + fld.l 0(%r0),%f0 + fld.l 124(%r1),%f31 + fld.l 256(%r2),%f30 + fld.l 512(%r3),%f29 + fld.l 1024(%r4),%f28 + fld.l 4096(%r5),%f27 + fld.l 8192(%r6),%f26 + fld.l 16384(%r7),%f25 + fld.l 32764(%r7),%f25 + fld.l -32768(%r7),%f23 + fld.l -16384(%r8),%f2 + fld.l -8192(%r9),%f3 + fld.l -4096(%r10),%f8 + fld.l -1024(%r11),%f9 + fld.l -508(%r12),%f12 + fld.l -248(%r13),%f19 + fld.l -4(%r14),%f21 + + # Immediate form, with auto-increment. + fld.l 0(%r0)++,%f0 + fld.l 124(%r1)++,%f1 + fld.l 256(%r2)++,%f2 + fld.l 512(%r3)++,%f3 + fld.l 1024(%r4)++,%f4 + fld.l 4096(%r5)++,%f5 + fld.l 8192(%r6)++,%f6 + fld.l 16384(%r7)++,%f7 + fld.l 32764(%r7)++,%f8 + fld.l -32768(%r7)++,%f9 + fld.l -16384(%r8)++,%f10 + fld.l -8192(%r9)++,%f11 + fld.l -4096(%r10)++,%f12 + fld.l -1024(%r11)++,%f13 + fld.l -508(%r12)++,%f14 + fld.l -248(%r13)++,%f15 + fld.l -4(%r14)++,%f16 + + # Index form, no auto-increment. + fld.l %r5(%r0),%f0 + fld.l %r6(%r1),%f31 + fld.l %r7(%r2),%f30 + fld.l %r8(%r3),%f29 + fld.l %r9(%r4),%f28 + fld.l %r0(%r5),%f27 + fld.l %r1(%r6),%f26 + fld.l %r12(%r7),%f25 + fld.l %r13(%r8),%f24 + fld.l %r14(%r9),%f23 + fld.l %r15(%r10),%f22 + fld.l %r16(%r11),%f21 + fld.l %r17(%r12),%f20 + fld.l %r28(%r13),%f19 + fld.l %r31(%r14),%f18 + + # Index form, with auto-increment. + fld.l %r5(%r0)++,%f0 + fld.l %r6(%r1)++,%f1 + fld.l %r7(%r2)++,%f2 + fld.l %r8(%r3)++,%f3 + fld.l %r9(%r4)++,%f4 + fld.l %r0(%r5)++,%f5 + fld.l %r1(%r6)++,%f6 + fld.l %r12(%r7)++,%f7 + fld.l %r13(%r8)++,%f8 + fld.l %r14(%r9)++,%f9 + fld.l %r15(%r10)++,%f10 + fld.l %r16(%r11)++,%f11 + fld.l %r17(%r12)++,%f12 + fld.l %r28(%r13)++,%f13 + fld.l %r31(%r14)++,%f14 + diff --git a/gas/testsuite/gas/i860/fldst02.d b/gas/testsuite/gas/i860/fldst02.d new file mode 100644 index 00000000000..7a0db945183 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst02.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst02 (fld.d) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 24 fld.d 0\(%r0\),%f0 + 4: 80 00 3e 24 fld.d 128\(%r1\),%f30 + 8: 00 01 5c 24 fld.d 256\(%sp\),%f28 + c: 00 02 7a 24 fld.d 512\(%fp\),%f26 + 10: 00 04 98 24 fld.d 1024\(%r4\),%f24 + 14: 00 10 b6 24 fld.d 4096\(%r5\),%f22 + 18: 00 20 d4 24 fld.d 8192\(%r6\),%f20 + 1c: 00 40 f2 24 fld.d 16384\(%r7\),%f18 + 20: f8 7f f0 24 fld.d 32760\(%r7\),%f16 + 24: 00 80 ee 24 fld.d -32768\(%r7\),%f14 + 28: 00 c0 0c 25 fld.d -16384\(%r8\),%f12 + 2c: 00 e0 2a 25 fld.d -8192\(%r9\),%f10 + 30: 00 f0 48 25 fld.d -4096\(%r10\),%f8 + 34: 00 fc 66 25 fld.d -1024\(%r11\),%f6 + 38: 00 fe 84 25 fld.d -512\(%r12\),%f4 + 3c: 08 ff a2 25 fld.d -248\(%r13\),%f2 + 40: f8 ff c0 25 fld.d -8\(%r14\),%f0 + 44: 01 00 00 24 fld.d 0\(%r0\)\+\+,%f0 + 48: 81 00 22 24 fld.d 128\(%r1\)\+\+,%f2 + 4c: 01 01 44 24 fld.d 256\(%sp\)\+\+,%f4 + 50: 01 02 66 24 fld.d 512\(%fp\)\+\+,%f6 + 54: 01 04 88 24 fld.d 1024\(%r4\)\+\+,%f8 + 58: 01 10 aa 24 fld.d 4096\(%r5\)\+\+,%f10 + 5c: 01 20 cc 24 fld.d 8192\(%r6\)\+\+,%f12 + 60: 01 40 ee 24 fld.d 16384\(%r7\)\+\+,%f14 + 64: f9 7f f0 24 fld.d 32760\(%r7\)\+\+,%f16 + 68: 01 80 f2 24 fld.d -32768\(%r7\)\+\+,%f18 + 6c: 01 c0 14 25 fld.d -16384\(%r8\)\+\+,%f20 + 70: 01 e0 36 25 fld.d -8192\(%r9\)\+\+,%f22 + 74: 01 f0 58 25 fld.d -4096\(%r10\)\+\+,%f24 + 78: 01 fc 7a 25 fld.d -1024\(%r11\)\+\+,%f26 + 7c: 01 fe 9c 25 fld.d -512\(%r12\)\+\+,%f28 + 80: 09 ff be 25 fld.d -248\(%r13\)\+\+,%f30 + 84: f9 ff d0 25 fld.d -8\(%r14\)\+\+,%f16 + 88: 00 28 00 20 fld.d %r5\(%r0\),%f0 + 8c: 00 30 3e 20 fld.d %r6\(%r1\),%f30 + 90: 00 38 5c 20 fld.d %r7\(%sp\),%f28 + 94: 00 40 7a 20 fld.d %r8\(%fp\),%f26 + 98: 00 48 98 20 fld.d %r9\(%r4\),%f24 + 9c: 00 00 b6 20 fld.d %r0\(%r5\),%f22 + a0: 00 08 d4 20 fld.d %r1\(%r6\),%f20 + a4: 00 60 f2 20 fld.d %r12\(%r7\),%f18 + a8: 00 68 10 21 fld.d %r13\(%r8\),%f16 + ac: 00 70 2e 21 fld.d %r14\(%r9\),%f14 + b0: 00 78 4c 21 fld.d %r15\(%r10\),%f12 + b4: 00 80 6a 21 fld.d %r16\(%r11\),%f10 + b8: 00 88 88 21 fld.d %r17\(%r12\),%f8 + bc: 00 e0 a6 21 fld.d %r28\(%r13\),%f6 + c0: 00 f8 c4 21 fld.d %r31\(%r14\),%f4 + c4: 01 28 00 20 fld.d %r5\(%r0\)\+\+,%f0 + c8: 01 30 22 20 fld.d %r6\(%r1\)\+\+,%f2 + cc: 01 38 44 20 fld.d %r7\(%sp\)\+\+,%f4 + d0: 01 40 66 20 fld.d %r8\(%fp\)\+\+,%f6 + d4: 01 48 88 20 fld.d %r9\(%r4\)\+\+,%f8 + d8: 01 00 aa 20 fld.d %r0\(%r5\)\+\+,%f10 + dc: 01 08 cc 20 fld.d %r1\(%r6\)\+\+,%f12 + e0: 01 60 ee 20 fld.d %r12\(%r7\)\+\+,%f14 + e4: 01 68 10 21 fld.d %r13\(%r8\)\+\+,%f16 + e8: 01 70 32 21 fld.d %r14\(%r9\)\+\+,%f18 + ec: 01 78 54 21 fld.d %r15\(%r10\)\+\+,%f20 + f0: 01 80 76 21 fld.d %r16\(%r11\)\+\+,%f22 + f4: 01 88 98 21 fld.d %r17\(%r12\)\+\+,%f24 + f8: 01 e0 ba 21 fld.d %r28\(%r13\)\+\+,%f26 + fc: 01 f8 de 21 fld.d %r31\(%r14\)\+\+,%f30 diff --git a/gas/testsuite/gas/i860/fldst02.s b/gas/testsuite/gas/i860/fldst02.s new file mode 100644 index 00000000000..50b612b3793 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst02.s @@ -0,0 +1,75 @@ +# fld.d (no relocations here) + .text + + # Immediate form, no auto-increment. + fld.d 0(%r0),%f0 + fld.d 128(%r1),%f30 + fld.d 256(%r2),%f28 + fld.d 512(%r3),%f26 + fld.d 1024(%r4),%f24 + fld.d 4096(%r5),%f22 + fld.d 8192(%r6),%f20 + fld.d 16384(%r7),%f18 + fld.d 32760(%r7),%f16 + fld.d -32768(%r7),%f14 + fld.d -16384(%r8),%f12 + fld.d -8192(%r9),%f10 + fld.d -4096(%r10),%f8 + fld.d -1024(%r11),%f6 + fld.d -512(%r12),%f4 + fld.d -248(%r13),%f2 + fld.d -8(%r14),%f0 + + # Immediate form, with auto-increment. + fld.d 0(%r0)++,%f0 + fld.d 128(%r1)++,%f2 + fld.d 256(%r2)++,%f4 + fld.d 512(%r3)++,%f6 + fld.d 1024(%r4)++,%f8 + fld.d 4096(%r5)++,%f10 + fld.d 8192(%r6)++,%f12 + fld.d 16384(%r7)++,%f14 + fld.d 32760(%r7)++,%f16 + fld.d -32768(%r7)++,%f18 + fld.d -16384(%r8)++,%f20 + fld.d -8192(%r9)++,%f22 + fld.d -4096(%r10)++,%f24 + fld.d -1024(%r11)++,%f26 + fld.d -512(%r12)++,%f28 + fld.d -248(%r13)++,%f30 + fld.d -8(%r14)++,%f16 + + # Index form, no auto-increment. + fld.d %r5(%r0),%f0 + fld.d %r6(%r1),%f30 + fld.d %r7(%r2),%f28 + fld.d %r8(%r3),%f26 + fld.d %r9(%r4),%f24 + fld.d %r0(%r5),%f22 + fld.d %r1(%r6),%f20 + fld.d %r12(%r7),%f18 + fld.d %r13(%r8),%f16 + fld.d %r14(%r9),%f14 + fld.d %r15(%r10),%f12 + fld.d %r16(%r11),%f10 + fld.d %r17(%r12),%f8 + fld.d %r28(%r13),%f6 + fld.d %r31(%r14),%f4 + + # Index form, with auto-increment. + fld.d %r5(%r0)++,%f0 + fld.d %r6(%r1)++,%f2 + fld.d %r7(%r2)++,%f4 + fld.d %r8(%r3)++,%f6 + fld.d %r9(%r4)++,%f8 + fld.d %r0(%r5)++,%f10 + fld.d %r1(%r6)++,%f12 + fld.d %r12(%r7)++,%f14 + fld.d %r13(%r8)++,%f16 + fld.d %r14(%r9)++,%f18 + fld.d %r15(%r10)++,%f20 + fld.d %r16(%r11)++,%f22 + fld.d %r17(%r12)++,%f24 + fld.d %r28(%r13)++,%f26 + fld.d %r31(%r14)++,%f30 + diff --git a/gas/testsuite/gas/i860/fldst03.d b/gas/testsuite/gas/i860/fldst03.d new file mode 100644 index 00000000000..033c904feb0 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst03.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst03 (fld.q) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 04 00 00 24 fld.q 0\(%r0\),%f0 + 4: 84 00 3c 24 fld.q 128\(%r1\),%f28 + 8: 04 01 58 24 fld.q 256\(%sp\),%f24 + c: 04 02 74 24 fld.q 512\(%fp\),%f20 + 10: 04 04 90 24 fld.q 1024\(%r4\),%f16 + 14: 04 10 ac 24 fld.q 4096\(%r5\),%f12 + 18: 04 20 c8 24 fld.q 8192\(%r6\),%f8 + 1c: 04 40 e4 24 fld.q 16384\(%r7\),%f4 + 20: f4 7f e0 24 fld.q 32752\(%r7\),%f0 + 24: 04 80 fc 24 fld.q -32768\(%r7\),%f28 + 28: 04 c0 18 25 fld.q -16384\(%r8\),%f24 + 2c: 04 e0 34 25 fld.q -8192\(%r9\),%f20 + 30: 04 f0 50 25 fld.q -4096\(%r10\),%f16 + 34: 04 fc 6c 25 fld.q -1024\(%r11\),%f12 + 38: 04 fe 88 25 fld.q -512\(%r12\),%f8 + 3c: 04 ff a4 25 fld.q -256\(%r13\),%f4 + 40: f4 ff c0 25 fld.q -16\(%r14\),%f0 + 44: 05 00 00 24 fld.q 0\(%r0\)\+\+,%f0 + 48: 85 00 24 24 fld.q 128\(%r1\)\+\+,%f4 + 4c: 05 01 48 24 fld.q 256\(%sp\)\+\+,%f8 + 50: 05 02 6c 24 fld.q 512\(%fp\)\+\+,%f12 + 54: 05 04 90 24 fld.q 1024\(%r4\)\+\+,%f16 + 58: 05 10 b4 24 fld.q 4096\(%r5\)\+\+,%f20 + 5c: 05 20 d8 24 fld.q 8192\(%r6\)\+\+,%f24 + 60: 05 40 fc 24 fld.q 16384\(%r7\)\+\+,%f28 + 64: f5 7f e0 24 fld.q 32752\(%r7\)\+\+,%f0 + 68: 05 80 e4 24 fld.q -32768\(%r7\)\+\+,%f4 + 6c: 05 c0 08 25 fld.q -16384\(%r8\)\+\+,%f8 + 70: 05 e0 2c 25 fld.q -8192\(%r9\)\+\+,%f12 + 74: 05 f0 50 25 fld.q -4096\(%r10\)\+\+,%f16 + 78: 05 fc 74 25 fld.q -1024\(%r11\)\+\+,%f20 + 7c: 05 fe 98 25 fld.q -512\(%r12\)\+\+,%f24 + 80: 05 ff bc 25 fld.q -256\(%r13\)\+\+,%f28 + 84: f5 ff d0 25 fld.q -16\(%r14\)\+\+,%f16 + 88: 04 28 00 20 fld.q %r5\(%r0\),%f0 + 8c: 04 30 34 20 fld.q %r6\(%r1\),%f20 + 90: 04 38 50 20 fld.q %r7\(%sp\),%f16 + 94: 04 40 6c 20 fld.q %r8\(%fp\),%f12 + 98: 04 48 88 20 fld.q %r9\(%r4\),%f8 + 9c: 04 00 a4 20 fld.q %r0\(%r5\),%f4 + a0: 04 08 c0 20 fld.q %r1\(%r6\),%f0 + a4: 04 60 fc 20 fld.q %r12\(%r7\),%f28 + a8: 04 68 18 21 fld.q %r13\(%r8\),%f24 + ac: 04 70 34 21 fld.q %r14\(%r9\),%f20 + b0: 04 78 50 21 fld.q %r15\(%r10\),%f16 + b4: 04 80 6c 21 fld.q %r16\(%r11\),%f12 + b8: 04 88 88 21 fld.q %r17\(%r12\),%f8 + bc: 04 e0 a4 21 fld.q %r28\(%r13\),%f4 + c0: 04 f8 c0 21 fld.q %r31\(%r14\),%f0 + c4: 05 28 00 20 fld.q %r5\(%r0\)\+\+,%f0 + c8: 05 30 24 20 fld.q %r6\(%r1\)\+\+,%f4 + cc: 05 38 48 20 fld.q %r7\(%sp\)\+\+,%f8 + d0: 05 40 6c 20 fld.q %r8\(%fp\)\+\+,%f12 + d4: 05 48 90 20 fld.q %r9\(%r4\)\+\+,%f16 + d8: 05 00 b4 20 fld.q %r0\(%r5\)\+\+,%f20 + dc: 05 08 d8 20 fld.q %r1\(%r6\)\+\+,%f24 + e0: 05 60 fc 20 fld.q %r12\(%r7\)\+\+,%f28 + e4: 05 68 00 21 fld.q %r13\(%r8\)\+\+,%f0 + e8: 05 70 24 21 fld.q %r14\(%r9\)\+\+,%f4 + ec: 05 78 48 21 fld.q %r15\(%r10\)\+\+,%f8 + f0: 05 80 6c 21 fld.q %r16\(%r11\)\+\+,%f12 + f4: 05 88 90 21 fld.q %r17\(%r12\)\+\+,%f16 + f8: 05 e0 b4 21 fld.q %r28\(%r13\)\+\+,%f20 + fc: 05 f8 d8 21 fld.q %r31\(%r14\)\+\+,%f24 diff --git a/gas/testsuite/gas/i860/fldst03.s b/gas/testsuite/gas/i860/fldst03.s new file mode 100644 index 00000000000..7259925a7bb --- /dev/null +++ b/gas/testsuite/gas/i860/fldst03.s @@ -0,0 +1,75 @@ +# fld.q (no relocations here) + .text + + # Immediate form, no auto-increment. + fld.q 0(%r0),%f0 + fld.q 128(%r1),%f28 + fld.q 256(%r2),%f24 + fld.q 512(%r3),%f20 + fld.q 1024(%r4),%f16 + fld.q 4096(%r5),%f12 + fld.q 8192(%r6),%f8 + fld.q 16384(%r7),%f4 + fld.q 32752(%r7),%f0 + fld.q -32768(%r7),%f28 + fld.q -16384(%r8),%f24 + fld.q -8192(%r9),%f20 + fld.q -4096(%r10),%f16 + fld.q -1024(%r11),%f12 + fld.q -512(%r12),%f8 + fld.q -256(%r13),%f4 + fld.q -16(%r14),%f0 + + # Immediate form, with auto-increment. + fld.q 0(%r0)++,%f0 + fld.q 128(%r1)++,%f4 + fld.q 256(%r2)++,%f8 + fld.q 512(%r3)++,%f12 + fld.q 1024(%r4)++,%f16 + fld.q 4096(%r5)++,%f20 + fld.q 8192(%r6)++,%f24 + fld.q 16384(%r7)++,%f28 + fld.q 32752(%r7)++,%f0 + fld.q -32768(%r7)++,%f4 + fld.q -16384(%r8)++,%f8 + fld.q -8192(%r9)++,%f12 + fld.q -4096(%r10)++,%f16 + fld.q -1024(%r11)++,%f20 + fld.q -512(%r12)++,%f24 + fld.q -256(%r13)++,%f28 + fld.q -16(%r14)++,%f16 + + # Index form, no auto-increment. + fld.q %r5(%r0),%f0 + fld.q %r6(%r1),%f20 + fld.q %r7(%r2),%f16 + fld.q %r8(%r3),%f12 + fld.q %r9(%r4),%f8 + fld.q %r0(%r5),%f4 + fld.q %r1(%r6),%f0 + fld.q %r12(%r7),%f28 + fld.q %r13(%r8),%f24 + fld.q %r14(%r9),%f20 + fld.q %r15(%r10),%f16 + fld.q %r16(%r11),%f12 + fld.q %r17(%r12),%f8 + fld.q %r28(%r13),%f4 + fld.q %r31(%r14),%f0 + + # Index form, with auto-increment. + fld.q %r5(%r0)++,%f0 + fld.q %r6(%r1)++,%f4 + fld.q %r7(%r2)++,%f8 + fld.q %r8(%r3)++,%f12 + fld.q %r9(%r4)++,%f16 + fld.q %r0(%r5)++,%f20 + fld.q %r1(%r6)++,%f24 + fld.q %r12(%r7)++,%f28 + fld.q %r13(%r8)++,%f0 + fld.q %r14(%r9)++,%f4 + fld.q %r15(%r10)++,%f8 + fld.q %r16(%r11)++,%f12 + fld.q %r17(%r12)++,%f16 + fld.q %r28(%r13)++,%f20 + fld.q %r31(%r14)++,%f24 + diff --git a/gas/testsuite/gas/i860/fldst04.d b/gas/testsuite/gas/i860/fldst04.d new file mode 100644 index 00000000000..32559ce3a67 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst04.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst04 (fst.l) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 02 00 00 2c fst.l %f0,0\(%r0\) + 4: 7e 00 3f 2c fst.l %f31,124\(%r1\) + 8: 02 01 5e 2c fst.l %f30,256\(%sp\) + c: 02 02 7d 2c fst.l %f29,512\(%fp\) + 10: 02 04 9c 2c fst.l %f28,1024\(%r4\) + 14: 02 10 bb 2c fst.l %f27,4096\(%r5\) + 18: 02 20 da 2c fst.l %f26,8192\(%r6\) + 1c: 02 40 f9 2c fst.l %f25,16384\(%r7\) + 20: fe 7f f9 2c fst.l %f25,32764\(%r7\) + 24: 02 80 f7 2c fst.l %f23,-32768\(%r7\) + 28: 02 c0 02 2d fst.l %f2,-16384\(%r8\) + 2c: 02 e0 23 2d fst.l %f3,-8192\(%r9\) + 30: 02 f0 48 2d fst.l %f8,-4096\(%r10\) + 34: 02 fc 69 2d fst.l %f9,-1024\(%r11\) + 38: 06 fe 8c 2d fst.l %f12,-508\(%r12\) + 3c: 0a ff b3 2d fst.l %f19,-248\(%r13\) + 40: fe ff d5 2d fst.l %f21,-4\(%r14\) + 44: 03 00 00 2c fst.l %f0,0\(%r0\)\+\+ + 48: 7f 00 21 2c fst.l %f1,124\(%r1\)\+\+ + 4c: 03 01 42 2c fst.l %f2,256\(%sp\)\+\+ + 50: 03 02 63 2c fst.l %f3,512\(%fp\)\+\+ + 54: 03 04 84 2c fst.l %f4,1024\(%r4\)\+\+ + 58: 03 10 a5 2c fst.l %f5,4096\(%r5\)\+\+ + 5c: 03 20 c6 2c fst.l %f6,8192\(%r6\)\+\+ + 60: 03 40 e7 2c fst.l %f7,16384\(%r7\)\+\+ + 64: ff 7f e8 2c fst.l %f8,32764\(%r7\)\+\+ + 68: 03 80 e9 2c fst.l %f9,-32768\(%r7\)\+\+ + 6c: 03 c0 0a 2d fst.l %f10,-16384\(%r8\)\+\+ + 70: 03 e0 2b 2d fst.l %f11,-8192\(%r9\)\+\+ + 74: 03 f0 4c 2d fst.l %f12,-4096\(%r10\)\+\+ + 78: 03 fc 6d 2d fst.l %f13,-1024\(%r11\)\+\+ + 7c: 07 fe 8e 2d fst.l %f14,-508\(%r12\)\+\+ + 80: 0b ff af 2d fst.l %f15,-248\(%r13\)\+\+ + 84: ff ff d0 2d fst.l %f16,-4\(%r14\)\+\+ + 88: 02 28 00 28 fst.l %f0,%r5\(%r0\) + 8c: 02 30 3f 28 fst.l %f31,%r6\(%r1\) + 90: 02 38 5e 28 fst.l %f30,%r7\(%sp\) + 94: 02 40 7d 28 fst.l %f29,%r8\(%fp\) + 98: 02 48 9c 28 fst.l %f28,%r9\(%r4\) + 9c: 02 00 bb 28 fst.l %f27,%r0\(%r5\) + a0: 02 08 da 28 fst.l %f26,%r1\(%r6\) + a4: 02 60 f9 28 fst.l %f25,%r12\(%r7\) + a8: 02 68 18 29 fst.l %f24,%r13\(%r8\) + ac: 02 70 37 29 fst.l %f23,%r14\(%r9\) + b0: 02 78 56 29 fst.l %f22,%r15\(%r10\) + b4: 02 80 75 29 fst.l %f21,%r16\(%r11\) + b8: 02 88 94 29 fst.l %f20,%r17\(%r12\) + bc: 02 e0 b3 29 fst.l %f19,%r28\(%r13\) + c0: 02 f8 d2 29 fst.l %f18,%r31\(%r14\) + c4: 03 28 00 28 fst.l %f0,%r5\(%r0\)\+\+ + c8: 03 30 21 28 fst.l %f1,%r6\(%r1\)\+\+ + cc: 03 38 42 28 fst.l %f2,%r7\(%sp\)\+\+ + d0: 03 40 63 28 fst.l %f3,%r8\(%fp\)\+\+ + d4: 03 48 84 28 fst.l %f4,%r9\(%r4\)\+\+ + d8: 03 00 a5 28 fst.l %f5,%r0\(%r5\)\+\+ + dc: 03 08 c6 28 fst.l %f6,%r1\(%r6\)\+\+ + e0: 03 60 e7 28 fst.l %f7,%r12\(%r7\)\+\+ + e4: 03 68 08 29 fst.l %f8,%r13\(%r8\)\+\+ + e8: 03 70 29 29 fst.l %f9,%r14\(%r9\)\+\+ + ec: 03 78 4a 29 fst.l %f10,%r15\(%r10\)\+\+ + f0: 03 80 6b 29 fst.l %f11,%r16\(%r11\)\+\+ + f4: 03 88 8c 29 fst.l %f12,%r17\(%r12\)\+\+ + f8: 03 e0 ad 29 fst.l %f13,%r28\(%r13\)\+\+ + fc: 03 f8 ce 29 fst.l %f14,%r31\(%r14\)\+\+ diff --git a/gas/testsuite/gas/i860/fldst04.s b/gas/testsuite/gas/i860/fldst04.s new file mode 100644 index 00000000000..71366145738 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst04.s @@ -0,0 +1,75 @@ +# fst.l (no relocations here) + .text + + # Immediate form, no auto-increment. + fst.l %f0,0(%r0) + fst.l %f31,124(%r1) + fst.l %f30,256(%r2) + fst.l %f29,512(%r3) + fst.l %f28,1024(%r4) + fst.l %f27,4096(%r5) + fst.l %f26,8192(%r6) + fst.l %f25,16384(%r7) + fst.l %f25,32764(%r7) + fst.l %f23,-32768(%r7) + fst.l %f2,-16384(%r8) + fst.l %f3,-8192(%r9) + fst.l %f8,-4096(%r10) + fst.l %f9,-1024(%r11) + fst.l %f12,-508(%r12) + fst.l %f19,-248(%r13) + fst.l %f21,-4(%r14) + + # Immediate form, with auto-increment. + fst.l %f0,0(%r0)++ + fst.l %f1,124(%r1)++ + fst.l %f2,256(%r2)++ + fst.l %f3,512(%r3)++ + fst.l %f4,1024(%r4)++ + fst.l %f5,4096(%r5)++ + fst.l %f6,8192(%r6)++ + fst.l %f7,16384(%r7)++ + fst.l %f8,32764(%r7)++ + fst.l %f9,-32768(%r7)++ + fst.l %f10,-16384(%r8)++ + fst.l %f11,-8192(%r9)++ + fst.l %f12,-4096(%r10)++ + fst.l %f13,-1024(%r11)++ + fst.l %f14,-508(%r12)++ + fst.l %f15,-248(%r13)++ + fst.l %f16,-4(%r14)++ + + # Index form, no auto-increment. + fst.l %f0,%r5(%r0) + fst.l %f31,%r6(%r1) + fst.l %f30,%r7(%r2) + fst.l %f29,%r8(%r3) + fst.l %f28,%r9(%r4) + fst.l %f27,%r0(%r5) + fst.l %f26,%r1(%r6) + fst.l %f25,%r12(%r7) + fst.l %f24,%r13(%r8) + fst.l %f23,%r14(%r9) + fst.l %f22,%r15(%r10) + fst.l %f21,%r16(%r11) + fst.l %f20,%r17(%r12) + fst.l %f19,%r28(%r13) + fst.l %f18,%r31(%r14) + + # Index form, with auto-increment. + fst.l %f0,%r5(%r0)++ + fst.l %f1,%r6(%r1)++ + fst.l %f2,%r7(%r2)++ + fst.l %f3,%r8(%r3)++ + fst.l %f4,%r9(%r4)++ + fst.l %f5,%r0(%r5)++ + fst.l %f6,%r1(%r6)++ + fst.l %f7,%r12(%r7)++ + fst.l %f8,%r13(%r8)++ + fst.l %f9,%r14(%r9)++ + fst.l %f10,%r15(%r10)++ + fst.l %f11,%r16(%r11)++ + fst.l %f12,%r17(%r12)++ + fst.l %f13,%r28(%r13)++ + fst.l %f14,%r31(%r14)++ + diff --git a/gas/testsuite/gas/i860/fldst05.d b/gas/testsuite/gas/i860/fldst05.d new file mode 100644 index 00000000000..a6187bf361f --- /dev/null +++ b/gas/testsuite/gas/i860/fldst05.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst05 (fst.d) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 2c fst.d %f0,0\(%r0\) + 4: 80 00 3e 2c fst.d %f30,128\(%r1\) + 8: 00 01 5c 2c fst.d %f28,256\(%sp\) + c: 00 02 7a 2c fst.d %f26,512\(%fp\) + 10: 00 04 98 2c fst.d %f24,1024\(%r4\) + 14: 00 10 b6 2c fst.d %f22,4096\(%r5\) + 18: 00 20 d4 2c fst.d %f20,8192\(%r6\) + 1c: 00 40 f2 2c fst.d %f18,16384\(%r7\) + 20: f8 7f f0 2c fst.d %f16,32760\(%r7\) + 24: 00 80 ee 2c fst.d %f14,-32768\(%r7\) + 28: 00 c0 0c 2d fst.d %f12,-16384\(%r8\) + 2c: 00 e0 2a 2d fst.d %f10,-8192\(%r9\) + 30: 00 f0 48 2d fst.d %f8,-4096\(%r10\) + 34: 00 fc 66 2d fst.d %f6,-1024\(%r11\) + 38: 00 fe 84 2d fst.d %f4,-512\(%r12\) + 3c: 08 ff a2 2d fst.d %f2,-248\(%r13\) + 40: f8 ff c0 2d fst.d %f0,-8\(%r14\) + 44: 01 00 00 2c fst.d %f0,0\(%r0\)\+\+ + 48: 81 00 22 2c fst.d %f2,128\(%r1\)\+\+ + 4c: 01 01 44 2c fst.d %f4,256\(%sp\)\+\+ + 50: 01 02 66 2c fst.d %f6,512\(%fp\)\+\+ + 54: 01 04 88 2c fst.d %f8,1024\(%r4\)\+\+ + 58: 01 10 aa 2c fst.d %f10,4096\(%r5\)\+\+ + 5c: 01 20 cc 2c fst.d %f12,8192\(%r6\)\+\+ + 60: 01 40 ee 2c fst.d %f14,16384\(%r7\)\+\+ + 64: f9 7f f0 2c fst.d %f16,32760\(%r7\)\+\+ + 68: 01 80 f2 2c fst.d %f18,-32768\(%r7\)\+\+ + 6c: 01 c0 14 2d fst.d %f20,-16384\(%r8\)\+\+ + 70: 01 e0 36 2d fst.d %f22,-8192\(%r9\)\+\+ + 74: 01 f0 58 2d fst.d %f24,-4096\(%r10\)\+\+ + 78: 01 fc 7a 2d fst.d %f26,-1024\(%r11\)\+\+ + 7c: 01 fe 9c 2d fst.d %f28,-512\(%r12\)\+\+ + 80: 09 ff be 2d fst.d %f30,-248\(%r13\)\+\+ + 84: f9 ff d0 2d fst.d %f16,-8\(%r14\)\+\+ + 88: 00 28 00 28 fst.d %f0,%r5\(%r0\) + 8c: 00 30 3e 28 fst.d %f30,%r6\(%r1\) + 90: 00 38 5c 28 fst.d %f28,%r7\(%sp\) + 94: 00 40 7a 28 fst.d %f26,%r8\(%fp\) + 98: 00 48 98 28 fst.d %f24,%r9\(%r4\) + 9c: 00 00 b6 28 fst.d %f22,%r0\(%r5\) + a0: 00 08 d4 28 fst.d %f20,%r1\(%r6\) + a4: 00 60 f2 28 fst.d %f18,%r12\(%r7\) + a8: 00 68 10 29 fst.d %f16,%r13\(%r8\) + ac: 00 70 2e 29 fst.d %f14,%r14\(%r9\) + b0: 00 78 4c 29 fst.d %f12,%r15\(%r10\) + b4: 00 80 6a 29 fst.d %f10,%r16\(%r11\) + b8: 00 88 88 29 fst.d %f8,%r17\(%r12\) + bc: 00 e0 a6 29 fst.d %f6,%r28\(%r13\) + c0: 00 f8 c4 29 fst.d %f4,%r31\(%r14\) + c4: 01 28 00 28 fst.d %f0,%r5\(%r0\)\+\+ + c8: 01 30 22 28 fst.d %f2,%r6\(%r1\)\+\+ + cc: 01 38 44 28 fst.d %f4,%r7\(%sp\)\+\+ + d0: 01 40 66 28 fst.d %f6,%r8\(%fp\)\+\+ + d4: 01 48 88 28 fst.d %f8,%r9\(%r4\)\+\+ + d8: 01 00 aa 28 fst.d %f10,%r0\(%r5\)\+\+ + dc: 01 08 cc 28 fst.d %f12,%r1\(%r6\)\+\+ + e0: 01 60 ee 28 fst.d %f14,%r12\(%r7\)\+\+ + e4: 01 68 10 29 fst.d %f16,%r13\(%r8\)\+\+ + e8: 01 70 32 29 fst.d %f18,%r14\(%r9\)\+\+ + ec: 01 78 54 29 fst.d %f20,%r15\(%r10\)\+\+ + f0: 01 80 76 29 fst.d %f22,%r16\(%r11\)\+\+ + f4: 01 88 98 29 fst.d %f24,%r17\(%r12\)\+\+ + f8: 01 e0 ba 29 fst.d %f26,%r28\(%r13\)\+\+ + fc: 01 f8 de 29 fst.d %f30,%r31\(%r14\)\+\+ diff --git a/gas/testsuite/gas/i860/fldst05.s b/gas/testsuite/gas/i860/fldst05.s new file mode 100644 index 00000000000..97032aa3b5a --- /dev/null +++ b/gas/testsuite/gas/i860/fldst05.s @@ -0,0 +1,75 @@ +# fst.d (no relocations here) + .text + + # Immediate form, no auto-increment. + fst.d %f0,0(%r0) + fst.d %f30,128(%r1) + fst.d %f28,256(%r2) + fst.d %f26,512(%r3) + fst.d %f24,1024(%r4) + fst.d %f22,4096(%r5) + fst.d %f20,8192(%r6) + fst.d %f18,16384(%r7) + fst.d %f16,32760(%r7) + fst.d %f14,-32768(%r7) + fst.d %f12,-16384(%r8) + fst.d %f10,-8192(%r9) + fst.d %f8,-4096(%r10) + fst.d %f6,-1024(%r11) + fst.d %f4,-512(%r12) + fst.d %f2,-248(%r13) + fst.d %f0,-8(%r14) + + # Immediate form, with auto-increment. + fst.d %f0,0(%r0)++ + fst.d %f2,128(%r1)++ + fst.d %f4,256(%r2)++ + fst.d %f6,512(%r3)++ + fst.d %f8,1024(%r4)++ + fst.d %f10,4096(%r5)++ + fst.d %f12,8192(%r6)++ + fst.d %f14,16384(%r7)++ + fst.d %f16,32760(%r7)++ + fst.d %f18,-32768(%r7)++ + fst.d %f20,-16384(%r8)++ + fst.d %f22,-8192(%r9)++ + fst.d %f24,-4096(%r10)++ + fst.d %f26,-1024(%r11)++ + fst.d %f28,-512(%r12)++ + fst.d %f30,-248(%r13)++ + fst.d %f16,-8(%r14)++ + + # Index form, no auto-increment. + fst.d %f0,%r5(%r0) + fst.d %f30,%r6(%r1) + fst.d %f28,%r7(%r2) + fst.d %f26,%r8(%r3) + fst.d %f24,%r9(%r4) + fst.d %f22,%r0(%r5) + fst.d %f20,%r1(%r6) + fst.d %f18,%r12(%r7) + fst.d %f16,%r13(%r8) + fst.d %f14,%r14(%r9) + fst.d %f12,%r15(%r10) + fst.d %f10,%r16(%r11) + fst.d %f8,%r17(%r12) + fst.d %f6,%r28(%r13) + fst.d %f4,%r31(%r14) + + # Index form, with auto-increment. + fst.d %f0,%r5(%r0)++ + fst.d %f2,%r6(%r1)++ + fst.d %f4,%r7(%r2)++ + fst.d %f6,%r8(%r3)++ + fst.d %f8,%r9(%r4)++ + fst.d %f10,%r0(%r5)++ + fst.d %f12,%r1(%r6)++ + fst.d %f14,%r12(%r7)++ + fst.d %f16,%r13(%r8)++ + fst.d %f18,%r14(%r9)++ + fst.d %f20,%r15(%r10)++ + fst.d %f22,%r16(%r11)++ + fst.d %f24,%r17(%r12)++ + fst.d %f26,%r28(%r13)++ + fst.d %f30,%r31(%r14)++ + diff --git a/gas/testsuite/gas/i860/fldst06.d b/gas/testsuite/gas/i860/fldst06.d new file mode 100644 index 00000000000..a1f6c5c19fa --- /dev/null +++ b/gas/testsuite/gas/i860/fldst06.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst06 (fst.q) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 04 00 00 2c fst.q %f0,0\(%r0\) + 4: 84 00 3c 2c fst.q %f28,128\(%r1\) + 8: 04 01 58 2c fst.q %f24,256\(%sp\) + c: 04 02 74 2c fst.q %f20,512\(%fp\) + 10: 04 04 90 2c fst.q %f16,1024\(%r4\) + 14: 04 10 ac 2c fst.q %f12,4096\(%r5\) + 18: 04 20 c8 2c fst.q %f8,8192\(%r6\) + 1c: 04 40 e4 2c fst.q %f4,16384\(%r7\) + 20: f4 7f e0 2c fst.q %f0,32752\(%r7\) + 24: 04 80 fc 2c fst.q %f28,-32768\(%r7\) + 28: 04 c0 18 2d fst.q %f24,-16384\(%r8\) + 2c: 04 e0 34 2d fst.q %f20,-8192\(%r9\) + 30: 04 f0 50 2d fst.q %f16,-4096\(%r10\) + 34: 04 fc 6c 2d fst.q %f12,-1024\(%r11\) + 38: 04 fe 88 2d fst.q %f8,-512\(%r12\) + 3c: 04 ff a4 2d fst.q %f4,-256\(%r13\) + 40: f4 ff c0 2d fst.q %f0,-16\(%r14\) + 44: 05 00 00 2c fst.q %f0,0\(%r0\)\+\+ + 48: 85 00 24 2c fst.q %f4,128\(%r1\)\+\+ + 4c: 05 01 48 2c fst.q %f8,256\(%sp\)\+\+ + 50: 05 02 6c 2c fst.q %f12,512\(%fp\)\+\+ + 54: 05 04 90 2c fst.q %f16,1024\(%r4\)\+\+ + 58: 05 10 b4 2c fst.q %f20,4096\(%r5\)\+\+ + 5c: 05 20 d8 2c fst.q %f24,8192\(%r6\)\+\+ + 60: 05 40 fc 2c fst.q %f28,16384\(%r7\)\+\+ + 64: f5 7f e0 2c fst.q %f0,32752\(%r7\)\+\+ + 68: 05 80 e4 2c fst.q %f4,-32768\(%r7\)\+\+ + 6c: 05 c0 08 2d fst.q %f8,-16384\(%r8\)\+\+ + 70: 05 e0 2c 2d fst.q %f12,-8192\(%r9\)\+\+ + 74: 05 f0 50 2d fst.q %f16,-4096\(%r10\)\+\+ + 78: 05 fc 74 2d fst.q %f20,-1024\(%r11\)\+\+ + 7c: 05 fe 98 2d fst.q %f24,-512\(%r12\)\+\+ + 80: 05 ff bc 2d fst.q %f28,-256\(%r13\)\+\+ + 84: f5 ff d0 2d fst.q %f16,-16\(%r14\)\+\+ + 88: 04 28 00 28 fst.q %f0,%r5\(%r0\) + 8c: 04 30 34 28 fst.q %f20,%r6\(%r1\) + 90: 04 38 50 28 fst.q %f16,%r7\(%sp\) + 94: 04 40 6c 28 fst.q %f12,%r8\(%fp\) + 98: 04 48 88 28 fst.q %f8,%r9\(%r4\) + 9c: 04 00 a4 28 fst.q %f4,%r0\(%r5\) + a0: 04 08 c0 28 fst.q %f0,%r1\(%r6\) + a4: 04 60 fc 28 fst.q %f28,%r12\(%r7\) + a8: 04 68 18 29 fst.q %f24,%r13\(%r8\) + ac: 04 70 34 29 fst.q %f20,%r14\(%r9\) + b0: 04 78 50 29 fst.q %f16,%r15\(%r10\) + b4: 04 80 6c 29 fst.q %f12,%r16\(%r11\) + b8: 04 88 88 29 fst.q %f8,%r17\(%r12\) + bc: 04 e0 a4 29 fst.q %f4,%r28\(%r13\) + c0: 04 f8 c0 29 fst.q %f0,%r31\(%r14\) + c4: 05 28 00 28 fst.q %f0,%r5\(%r0\)\+\+ + c8: 05 30 24 28 fst.q %f4,%r6\(%r1\)\+\+ + cc: 05 38 48 28 fst.q %f8,%r7\(%sp\)\+\+ + d0: 05 40 6c 28 fst.q %f12,%r8\(%fp\)\+\+ + d4: 05 48 90 28 fst.q %f16,%r9\(%r4\)\+\+ + d8: 05 00 b4 28 fst.q %f20,%r0\(%r5\)\+\+ + dc: 05 08 d8 28 fst.q %f24,%r1\(%r6\)\+\+ + e0: 05 60 fc 28 fst.q %f28,%r12\(%r7\)\+\+ + e4: 05 68 00 29 fst.q %f0,%r13\(%r8\)\+\+ + e8: 05 70 24 29 fst.q %f4,%r14\(%r9\)\+\+ + ec: 05 78 48 29 fst.q %f8,%r15\(%r10\)\+\+ + f0: 05 80 6c 29 fst.q %f12,%r16\(%r11\)\+\+ + f4: 05 88 90 29 fst.q %f16,%r17\(%r12\)\+\+ + f8: 05 e0 b4 29 fst.q %f20,%r28\(%r13\)\+\+ + fc: 05 f8 d8 29 fst.q %f24,%r31\(%r14\)\+\+ diff --git a/gas/testsuite/gas/i860/fldst06.s b/gas/testsuite/gas/i860/fldst06.s new file mode 100644 index 00000000000..0bb1476897b --- /dev/null +++ b/gas/testsuite/gas/i860/fldst06.s @@ -0,0 +1,75 @@ +# fst.q (no relocations here) + .text + + # Immediate form, no auto-increment. + fst.q %f0,0(%r0) + fst.q %f28,128(%r1) + fst.q %f24,256(%r2) + fst.q %f20,512(%r3) + fst.q %f16,1024(%r4) + fst.q %f12,4096(%r5) + fst.q %f8,8192(%r6) + fst.q %f4,16384(%r7) + fst.q %f0,32752(%r7) + fst.q %f28,-32768(%r7) + fst.q %f24,-16384(%r8) + fst.q %f20,-8192(%r9) + fst.q %f16,-4096(%r10) + fst.q %f12,-1024(%r11) + fst.q %f8,-512(%r12) + fst.q %f4,-256(%r13) + fst.q %f0,-16(%r14) + + # Immediate form, with auto-increment. + fst.q %f0,0(%r0)++ + fst.q %f4,128(%r1)++ + fst.q %f8,256(%r2)++ + fst.q %f12,512(%r3)++ + fst.q %f16,1024(%r4)++ + fst.q %f20,4096(%r5)++ + fst.q %f24,8192(%r6)++ + fst.q %f28,16384(%r7)++ + fst.q %f0,32752(%r7)++ + fst.q %f4,-32768(%r7)++ + fst.q %f8,-16384(%r8)++ + fst.q %f12,-8192(%r9)++ + fst.q %f16,-4096(%r10)++ + fst.q %f20,-1024(%r11)++ + fst.q %f24,-512(%r12)++ + fst.q %f28,-256(%r13)++ + fst.q %f16,-16(%r14)++ + + # Index form, no auto-increment. + fst.q %f0,%r5(%r0) + fst.q %f20,%r6(%r1) + fst.q %f16,%r7(%r2) + fst.q %f12,%r8(%r3) + fst.q %f8,%r9(%r4) + fst.q %f4,%r0(%r5) + fst.q %f0,%r1(%r6) + fst.q %f28,%r12(%r7) + fst.q %f24,%r13(%r8) + fst.q %f20,%r14(%r9) + fst.q %f16,%r15(%r10) + fst.q %f12,%r16(%r11) + fst.q %f8,%r17(%r12) + fst.q %f4,%r28(%r13) + fst.q %f0,%r31(%r14) + + # Index form, with auto-increment. + fst.q %f0,%r5(%r0)++ + fst.q %f4,%r6(%r1)++ + fst.q %f8,%r7(%r2)++ + fst.q %f12,%r8(%r3)++ + fst.q %f16,%r9(%r4)++ + fst.q %f20,%r0(%r5)++ + fst.q %f24,%r1(%r6)++ + fst.q %f28,%r12(%r7)++ + fst.q %f0,%r13(%r8)++ + fst.q %f4,%r14(%r9)++ + fst.q %f8,%r15(%r10)++ + fst.q %f12,%r16(%r11)++ + fst.q %f16,%r17(%r12)++ + fst.q %f20,%r28(%r13)++ + fst.q %f24,%r31(%r14)++ + diff --git a/gas/testsuite/gas/i860/fldst07.d b/gas/testsuite/gas/i860/fldst07.d new file mode 100644 index 00000000000..4ba66f9fd1f --- /dev/null +++ b/gas/testsuite/gas/i860/fldst07.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst07 (pfld.l) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 02 00 00 64 pfld.l 0\(%r0\),%f0 + 4: 7e 00 3f 64 pfld.l 124\(%r1\),%f31 + 8: 02 01 5e 64 pfld.l 256\(%sp\),%f30 + c: 02 02 7d 64 pfld.l 512\(%fp\),%f29 + 10: 02 04 9c 64 pfld.l 1024\(%r4\),%f28 + 14: 02 10 bb 64 pfld.l 4096\(%r5\),%f27 + 18: 02 20 da 64 pfld.l 8192\(%r6\),%f26 + 1c: 02 40 f9 64 pfld.l 16384\(%r7\),%f25 + 20: fe 7f f9 64 pfld.l 32764\(%r7\),%f25 + 24: 02 80 f7 64 pfld.l -32768\(%r7\),%f23 + 28: 02 c0 02 65 pfld.l -16384\(%r8\),%f2 + 2c: 02 e0 23 65 pfld.l -8192\(%r9\),%f3 + 30: 02 f0 48 65 pfld.l -4096\(%r10\),%f8 + 34: 02 fc 69 65 pfld.l -1024\(%r11\),%f9 + 38: 06 fe 8c 65 pfld.l -508\(%r12\),%f12 + 3c: 0a ff b3 65 pfld.l -248\(%r13\),%f19 + 40: fe ff d5 65 pfld.l -4\(%r14\),%f21 + 44: 03 00 00 64 pfld.l 0\(%r0\)\+\+,%f0 + 48: 7f 00 21 64 pfld.l 124\(%r1\)\+\+,%f1 + 4c: 03 01 42 64 pfld.l 256\(%sp\)\+\+,%f2 + 50: 03 02 63 64 pfld.l 512\(%fp\)\+\+,%f3 + 54: 03 04 84 64 pfld.l 1024\(%r4\)\+\+,%f4 + 58: 03 10 a5 64 pfld.l 4096\(%r5\)\+\+,%f5 + 5c: 03 20 c6 64 pfld.l 8192\(%r6\)\+\+,%f6 + 60: 03 40 e7 64 pfld.l 16384\(%r7\)\+\+,%f7 + 64: ff 7f e8 64 pfld.l 32764\(%r7\)\+\+,%f8 + 68: 03 80 e9 64 pfld.l -32768\(%r7\)\+\+,%f9 + 6c: 03 c0 0a 65 pfld.l -16384\(%r8\)\+\+,%f10 + 70: 03 e0 2b 65 pfld.l -8192\(%r9\)\+\+,%f11 + 74: 03 f0 4c 65 pfld.l -4096\(%r10\)\+\+,%f12 + 78: 03 fc 6d 65 pfld.l -1024\(%r11\)\+\+,%f13 + 7c: 07 fe 8e 65 pfld.l -508\(%r12\)\+\+,%f14 + 80: 0b ff af 65 pfld.l -248\(%r13\)\+\+,%f15 + 84: ff ff d0 65 pfld.l -4\(%r14\)\+\+,%f16 + 88: 02 28 00 60 pfld.l %r5\(%r0\),%f0 + 8c: 02 30 3f 60 pfld.l %r6\(%r1\),%f31 + 90: 02 38 5e 60 pfld.l %r7\(%sp\),%f30 + 94: 02 40 7d 60 pfld.l %r8\(%fp\),%f29 + 98: 02 48 9c 60 pfld.l %r9\(%r4\),%f28 + 9c: 02 00 bb 60 pfld.l %r0\(%r5\),%f27 + a0: 02 08 da 60 pfld.l %r1\(%r6\),%f26 + a4: 02 60 f9 60 pfld.l %r12\(%r7\),%f25 + a8: 02 68 18 61 pfld.l %r13\(%r8\),%f24 + ac: 02 70 37 61 pfld.l %r14\(%r9\),%f23 + b0: 02 78 56 61 pfld.l %r15\(%r10\),%f22 + b4: 02 80 75 61 pfld.l %r16\(%r11\),%f21 + b8: 02 88 94 61 pfld.l %r17\(%r12\),%f20 + bc: 02 e0 b3 61 pfld.l %r28\(%r13\),%f19 + c0: 02 f8 d2 61 pfld.l %r31\(%r14\),%f18 + c4: 03 28 00 60 pfld.l %r5\(%r0\)\+\+,%f0 + c8: 03 30 21 60 pfld.l %r6\(%r1\)\+\+,%f1 + cc: 03 38 42 60 pfld.l %r7\(%sp\)\+\+,%f2 + d0: 03 40 63 60 pfld.l %r8\(%fp\)\+\+,%f3 + d4: 03 48 84 60 pfld.l %r9\(%r4\)\+\+,%f4 + d8: 03 00 a5 60 pfld.l %r0\(%r5\)\+\+,%f5 + dc: 03 08 c6 60 pfld.l %r1\(%r6\)\+\+,%f6 + e0: 03 60 e7 60 pfld.l %r12\(%r7\)\+\+,%f7 + e4: 03 68 08 61 pfld.l %r13\(%r8\)\+\+,%f8 + e8: 03 70 29 61 pfld.l %r14\(%r9\)\+\+,%f9 + ec: 03 78 4a 61 pfld.l %r15\(%r10\)\+\+,%f10 + f0: 03 80 6b 61 pfld.l %r16\(%r11\)\+\+,%f11 + f4: 03 88 8c 61 pfld.l %r17\(%r12\)\+\+,%f12 + f8: 03 e0 ad 61 pfld.l %r28\(%r13\)\+\+,%f13 + fc: 03 f8 ce 61 pfld.l %r31\(%r14\)\+\+,%f14 diff --git a/gas/testsuite/gas/i860/fldst07.s b/gas/testsuite/gas/i860/fldst07.s new file mode 100644 index 00000000000..410b256e496 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst07.s @@ -0,0 +1,75 @@ +# pfld.l (no relocations here) + .text + + # Immediate form, no auto-increment. + pfld.l 0(%r0),%f0 + pfld.l 124(%r1),%f31 + pfld.l 256(%r2),%f30 + pfld.l 512(%r3),%f29 + pfld.l 1024(%r4),%f28 + pfld.l 4096(%r5),%f27 + pfld.l 8192(%r6),%f26 + pfld.l 16384(%r7),%f25 + pfld.l 32764(%r7),%f25 + pfld.l -32768(%r7),%f23 + pfld.l -16384(%r8),%f2 + pfld.l -8192(%r9),%f3 + pfld.l -4096(%r10),%f8 + pfld.l -1024(%r11),%f9 + pfld.l -508(%r12),%f12 + pfld.l -248(%r13),%f19 + pfld.l -4(%r14),%f21 + + # Immediate form, with auto-increment. + pfld.l 0(%r0)++,%f0 + pfld.l 124(%r1)++,%f1 + pfld.l 256(%r2)++,%f2 + pfld.l 512(%r3)++,%f3 + pfld.l 1024(%r4)++,%f4 + pfld.l 4096(%r5)++,%f5 + pfld.l 8192(%r6)++,%f6 + pfld.l 16384(%r7)++,%f7 + pfld.l 32764(%r7)++,%f8 + pfld.l -32768(%r7)++,%f9 + pfld.l -16384(%r8)++,%f10 + pfld.l -8192(%r9)++,%f11 + pfld.l -4096(%r10)++,%f12 + pfld.l -1024(%r11)++,%f13 + pfld.l -508(%r12)++,%f14 + pfld.l -248(%r13)++,%f15 + pfld.l -4(%r14)++,%f16 + + # Index form, no auto-increment. + pfld.l %r5(%r0),%f0 + pfld.l %r6(%r1),%f31 + pfld.l %r7(%r2),%f30 + pfld.l %r8(%r3),%f29 + pfld.l %r9(%r4),%f28 + pfld.l %r0(%r5),%f27 + pfld.l %r1(%r6),%f26 + pfld.l %r12(%r7),%f25 + pfld.l %r13(%r8),%f24 + pfld.l %r14(%r9),%f23 + pfld.l %r15(%r10),%f22 + pfld.l %r16(%r11),%f21 + pfld.l %r17(%r12),%f20 + pfld.l %r28(%r13),%f19 + pfld.l %r31(%r14),%f18 + + # Index form, with auto-increment. + pfld.l %r5(%r0)++,%f0 + pfld.l %r6(%r1)++,%f1 + pfld.l %r7(%r2)++,%f2 + pfld.l %r8(%r3)++,%f3 + pfld.l %r9(%r4)++,%f4 + pfld.l %r0(%r5)++,%f5 + pfld.l %r1(%r6)++,%f6 + pfld.l %r12(%r7)++,%f7 + pfld.l %r13(%r8)++,%f8 + pfld.l %r14(%r9)++,%f9 + pfld.l %r15(%r10)++,%f10 + pfld.l %r16(%r11)++,%f11 + pfld.l %r17(%r12)++,%f12 + pfld.l %r28(%r13)++,%f13 + pfld.l %r31(%r14)++,%f14 + diff --git a/gas/testsuite/gas/i860/fldst08.d b/gas/testsuite/gas/i860/fldst08.d new file mode 100644 index 00000000000..272b40d5ea2 --- /dev/null +++ b/gas/testsuite/gas/i860/fldst08.d @@ -0,0 +1,73 @@ +#as: +#objdump: -dr +#name: i860 fldst08 (pfld.d) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 64 pfld.d 0\(%r0\),%f0 + 4: 80 00 3e 64 pfld.d 128\(%r1\),%f30 + 8: 00 01 5c 64 pfld.d 256\(%sp\),%f28 + c: 00 02 7a 64 pfld.d 512\(%fp\),%f26 + 10: 00 04 98 64 pfld.d 1024\(%r4\),%f24 + 14: 00 10 b6 64 pfld.d 4096\(%r5\),%f22 + 18: 00 20 d4 64 pfld.d 8192\(%r6\),%f20 + 1c: 00 40 f2 64 pfld.d 16384\(%r7\),%f18 + 20: f8 7f f0 64 pfld.d 32760\(%r7\),%f16 + 24: 00 80 ee 64 pfld.d -32768\(%r7\),%f14 + 28: 00 c0 0c 65 pfld.d -16384\(%r8\),%f12 + 2c: 00 e0 2a 65 pfld.d -8192\(%r9\),%f10 + 30: 00 f0 48 65 pfld.d -4096\(%r10\),%f8 + 34: 00 fc 66 65 pfld.d -1024\(%r11\),%f6 + 38: 00 fe 84 65 pfld.d -512\(%r12\),%f4 + 3c: 08 ff a2 65 pfld.d -248\(%r13\),%f2 + 40: f8 ff c0 65 pfld.d -8\(%r14\),%f0 + 44: 01 00 00 64 pfld.d 0\(%r0\)\+\+,%f0 + 48: 81 00 22 64 pfld.d 128\(%r1\)\+\+,%f2 + 4c: 01 01 44 64 pfld.d 256\(%sp\)\+\+,%f4 + 50: 01 02 66 64 pfld.d 512\(%fp\)\+\+,%f6 + 54: 01 04 88 64 pfld.d 1024\(%r4\)\+\+,%f8 + 58: 01 10 aa 64 pfld.d 4096\(%r5\)\+\+,%f10 + 5c: 01 20 cc 64 pfld.d 8192\(%r6\)\+\+,%f12 + 60: 01 40 ee 64 pfld.d 16384\(%r7\)\+\+,%f14 + 64: f9 7f f0 64 pfld.d 32760\(%r7\)\+\+,%f16 + 68: 01 80 f2 64 pfld.d -32768\(%r7\)\+\+,%f18 + 6c: 01 c0 14 65 pfld.d -16384\(%r8\)\+\+,%f20 + 70: 01 e0 36 65 pfld.d -8192\(%r9\)\+\+,%f22 + 74: 01 f0 58 65 pfld.d -4096\(%r10\)\+\+,%f24 + 78: 01 fc 7a 65 pfld.d -1024\(%r11\)\+\+,%f26 + 7c: 01 fe 9c 65 pfld.d -512\(%r12\)\+\+,%f28 + 80: 09 ff be 65 pfld.d -248\(%r13\)\+\+,%f30 + 84: f9 ff d0 65 pfld.d -8\(%r14\)\+\+,%f16 + 88: 00 28 00 60 pfld.d %r5\(%r0\),%f0 + 8c: 00 30 3e 60 pfld.d %r6\(%r1\),%f30 + 90: 00 38 5c 60 pfld.d %r7\(%sp\),%f28 + 94: 00 40 7a 60 pfld.d %r8\(%fp\),%f26 + 98: 00 48 98 60 pfld.d %r9\(%r4\),%f24 + 9c: 00 00 b6 60 pfld.d %r0\(%r5\),%f22 + a0: 00 08 d4 60 pfld.d %r1\(%r6\),%f20 + a4: 00 60 f2 60 pfld.d %r12\(%r7\),%f18 + a8: 00 68 10 61 pfld.d %r13\(%r8\),%f16 + ac: 00 70 2e 61 pfld.d %r14\(%r9\),%f14 + b0: 00 78 4c 61 pfld.d %r15\(%r10\),%f12 + b4: 00 80 6a 61 pfld.d %r16\(%r11\),%f10 + b8: 00 88 88 61 pfld.d %r17\(%r12\),%f8 + bc: 00 e0 a6 61 pfld.d %r28\(%r13\),%f6 + c0: 00 f8 c4 61 pfld.d %r31\(%r14\),%f4 + c4: 01 28 00 60 pfld.d %r5\(%r0\)\+\+,%f0 + c8: 01 30 22 60 pfld.d %r6\(%r1\)\+\+,%f2 + cc: 01 38 44 60 pfld.d %r7\(%sp\)\+\+,%f4 + d0: 01 40 66 60 pfld.d %r8\(%fp\)\+\+,%f6 + d4: 01 48 88 60 pfld.d %r9\(%r4\)\+\+,%f8 + d8: 01 00 aa 60 pfld.d %r0\(%r5\)\+\+,%f10 + dc: 01 08 cc 60 pfld.d %r1\(%r6\)\+\+,%f12 + e0: 01 60 ee 60 pfld.d %r12\(%r7\)\+\+,%f14 + e4: 01 68 10 61 pfld.d %r13\(%r8\)\+\+,%f16 + e8: 01 70 32 61 pfld.d %r14\(%r9\)\+\+,%f18 + ec: 01 78 54 61 pfld.d %r15\(%r10\)\+\+,%f20 + f0: 01 80 76 61 pfld.d %r16\(%r11\)\+\+,%f22 + f4: 01 88 98 61 pfld.d %r17\(%r12\)\+\+,%f24 + f8: 01 e0 ba 61 pfld.d %r28\(%r13\)\+\+,%f26 + fc: 01 f8 de 61 pfld.d %r31\(%r14\)\+\+,%f30 diff --git a/gas/testsuite/gas/i860/fldst08.s b/gas/testsuite/gas/i860/fldst08.s new file mode 100644 index 00000000000..7ae6cf5174f --- /dev/null +++ b/gas/testsuite/gas/i860/fldst08.s @@ -0,0 +1,75 @@ +# pfld.d (no relocations here) + .text + + # Immediate form, no auto-increment. + pfld.d 0(%r0),%f0 + pfld.d 128(%r1),%f30 + pfld.d 256(%r2),%f28 + pfld.d 512(%r3),%f26 + pfld.d 1024(%r4),%f24 + pfld.d 4096(%r5),%f22 + pfld.d 8192(%r6),%f20 + pfld.d 16384(%r7),%f18 + pfld.d 32760(%r7),%f16 + pfld.d -32768(%r7),%f14 + pfld.d -16384(%r8),%f12 + pfld.d -8192(%r9),%f10 + pfld.d -4096(%r10),%f8 + pfld.d -1024(%r11),%f6 + pfld.d -512(%r12),%f4 + pfld.d -248(%r13),%f2 + pfld.d -8(%r14),%f0 + + # Immediate form, with auto-increment. + pfld.d 0(%r0)++,%f0 + pfld.d 128(%r1)++,%f2 + pfld.d 256(%r2)++,%f4 + pfld.d 512(%r3)++,%f6 + pfld.d 1024(%r4)++,%f8 + pfld.d 4096(%r5)++,%f10 + pfld.d 8192(%r6)++,%f12 + pfld.d 16384(%r7)++,%f14 + pfld.d 32760(%r7)++,%f16 + pfld.d -32768(%r7)++,%f18 + pfld.d -16384(%r8)++,%f20 + pfld.d -8192(%r9)++,%f22 + pfld.d -4096(%r10)++,%f24 + pfld.d -1024(%r11)++,%f26 + pfld.d -512(%r12)++,%f28 + pfld.d -248(%r13)++,%f30 + pfld.d -8(%r14)++,%f16 + + # Index form, no auto-increment. + pfld.d %r5(%r0),%f0 + pfld.d %r6(%r1),%f30 + pfld.d %r7(%r2),%f28 + pfld.d %r8(%r3),%f26 + pfld.d %r9(%r4),%f24 + pfld.d %r0(%r5),%f22 + pfld.d %r1(%r6),%f20 + pfld.d %r12(%r7),%f18 + pfld.d %r13(%r8),%f16 + pfld.d %r14(%r9),%f14 + pfld.d %r15(%r10),%f12 + pfld.d %r16(%r11),%f10 + pfld.d %r17(%r12),%f8 + pfld.d %r28(%r13),%f6 + pfld.d %r31(%r14),%f4 + + # Index form, with auto-increment. + pfld.d %r5(%r0)++,%f0 + pfld.d %r6(%r1)++,%f2 + pfld.d %r7(%r2)++,%f4 + pfld.d %r8(%r3)++,%f6 + pfld.d %r9(%r4)++,%f8 + pfld.d %r0(%r5)++,%f10 + pfld.d %r1(%r6)++,%f12 + pfld.d %r12(%r7)++,%f14 + pfld.d %r13(%r8)++,%f16 + pfld.d %r14(%r9)++,%f18 + pfld.d %r15(%r10)++,%f20 + pfld.d %r16(%r11)++,%f22 + pfld.d %r17(%r12)++,%f24 + pfld.d %r28(%r13)++,%f26 + pfld.d %r31(%r14)++,%f30 + diff --git a/gas/testsuite/gas/i860/float01.d b/gas/testsuite/gas/i860/float01.d new file mode 100644 index 00000000000..f614f1afbbf --- /dev/null +++ b/gas/testsuite/gas/i860/float01.d @@ -0,0 +1,69 @@ +#as: +#objdump: -dr +#name: i860 float01 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 30 00 22 48 fadd.ss %f0,%f1,%f2 + 4: b0 10 64 48 fadd.sd %f2,%f3,%f4 + 8: b0 31 0a 49 fadd.dd %f6,%f8,%f10 + c: 31 28 c7 48 fsub.ss %f5,%f6,%f7 + 10: b1 40 2a 49 fsub.sd %f8,%f9,%f10 + 14: b1 61 d0 49 fsub.dd %f12,%f14,%f16 + 18: 20 58 8d 49 fmul.ss %f11,%f12,%f13 + 1c: a0 70 f0 49 fmul.sd %f14,%f15,%f16 + 20: a0 91 96 4a fmul.dd %f18,%f20,%f22 + 24: a1 b1 1a 4b fmlow.dd %f22,%f24,%f26 + 28: 30 74 f0 49 pfadd.ss %f14,%f15,%f16 + 2c: b0 8c 54 4a pfadd.sd %f17,%f18,%f20 + 30: b0 b5 1a 4b pfadd.dd %f22,%f24,%f26 + 34: 31 a4 b6 4a pfsub.ss %f20,%f21,%f22 + 38: b1 bc 1a 4b pfsub.sd %f23,%f24,%f26 + 3c: b1 e5 c2 4b pfsub.dd %f28,%f30,%f2 + 40: 20 dc 9d 4b pfmul.ss %f27,%f28,%f29 + 44: a0 f4 e4 4b pfmul.sd %f30,%f31,%f4 + 48: a0 35 08 48 pfmul.dd %f6,%f0,%f8 + 4c: a4 15 9e 48 pfmul3.dd %f2,%f4,%f30 + 50: 30 02 22 48 d.fadd.ss %f0,%f1,%f2 + 54: 00 00 00 a0 shl %r0,%r0,%r0 + 58: b0 12 64 48 d.fadd.sd %f2,%f3,%f4 + 5c: 00 00 00 a0 shl %r0,%r0,%r0 + 60: b0 33 0a 49 d.fadd.dd %f6,%f8,%f10 + 64: 00 00 00 a0 shl %r0,%r0,%r0 + 68: 31 2a c7 48 d.fsub.ss %f5,%f6,%f7 + 6c: 00 00 00 a0 shl %r0,%r0,%r0 + 70: b1 42 2a 49 d.fsub.sd %f8,%f9,%f10 + 74: 00 00 00 a0 shl %r0,%r0,%r0 + 78: b1 63 d0 49 d.fsub.dd %f12,%f14,%f16 + 7c: 00 00 00 a0 shl %r0,%r0,%r0 + 80: 20 5a 8d 49 d.fmul.ss %f11,%f12,%f13 + 84: 00 00 00 a0 shl %r0,%r0,%r0 + 88: a0 72 f0 49 d.fmul.sd %f14,%f15,%f16 + 8c: 00 00 00 a0 shl %r0,%r0,%r0 + 90: a0 93 96 4a d.fmul.dd %f18,%f20,%f22 + 94: 00 00 00 a0 shl %r0,%r0,%r0 + 98: a1 43 4c 49 d.fmlow.dd %f8,%f10,%f12 + 9c: 00 00 00 a0 shl %r0,%r0,%r0 + a0: 30 76 f0 49 d.pfadd.ss %f14,%f15,%f16 + a4: 00 00 00 a0 shl %r0,%r0,%r0 + a8: b0 8e 54 4a d.pfadd.sd %f17,%f18,%f20 + ac: 00 00 00 a0 shl %r0,%r0,%r0 + b0: b0 b7 1a 4b d.pfadd.dd %f22,%f24,%f26 + b4: 00 00 00 a0 shl %r0,%r0,%r0 + b8: 31 a6 b6 4a d.pfsub.ss %f20,%f21,%f22 + bc: 00 00 00 a0 shl %r0,%r0,%r0 + c0: b1 be 1a 4b d.pfsub.sd %f23,%f24,%f26 + c4: 00 00 00 a0 shl %r0,%r0,%r0 + c8: b1 e7 c2 4b d.pfsub.dd %f28,%f30,%f2 + cc: 00 00 00 a0 shl %r0,%r0,%r0 + d0: 20 de 9d 4b d.pfmul.ss %f27,%f28,%f29 + d4: 00 00 00 a0 shl %r0,%r0,%r0 + d8: a0 f6 e4 4b d.pfmul.sd %f30,%f31,%f4 + dc: 00 00 00 a0 shl %r0,%r0,%r0 + e0: a0 37 08 48 d.pfmul.dd %f6,%f0,%f8 + e4: 00 00 00 a0 shl %r0,%r0,%r0 + e8: a4 17 9e 48 d.pfmul3.dd %f2,%f4,%f30 + ec: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/float01.s b/gas/testsuite/gas/i860/float01.s new file mode 100644 index 00000000000..88e3769a789 --- /dev/null +++ b/gas/testsuite/gas/i860/float01.s @@ -0,0 +1,84 @@ +# fadd, fsub, fmul, pfmul3, fmlow + + .text + + # Non-pipelined, without dual bit + fadd.ss %f0,%f1,%f2 + fadd.sd %f2,%f3,%f4 + fadd.dd %f6,%f8,%f10 + + fsub.ss %f5,%f6,%f7 + fsub.sd %f8,%f9,%f10 + fsub.dd %f12,%f14,%f16 + + fmul.ss %f11,%f12,%f13 + fmul.sd %f14,%f15,%f16 + fmul.dd %f18,%f20,%f22 + + fmlow.dd %f22,%f24,%f26 + + # Pipelined, without dual bit + pfadd.ss %f14,%f15,%f16 + pfadd.sd %f17,%f18,%f20 + pfadd.dd %f22,%f24,%f26 + + pfsub.ss %f20,%f21,%f22 + pfsub.sd %f23,%f24,%f26 + pfsub.dd %f28,%f30,%f2 + + pfmul.ss %f27,%f28,%f29 + pfmul.sd %f30,%f31,%f4 + pfmul.dd %f6,%f0,%f8 + + pfmul3.dd %f2,%f4,%f30 + + # Non-pipelined, with dual bit + d.fadd.ss %f0,%f1,%f2 + nop + d.fadd.sd %f2,%f3,%f4 + nop + d.fadd.dd %f6,%f8,%f10 + nop + + d.fsub.ss %f5,%f6,%f7 + nop + d.fsub.sd %f8,%f9,%f10 + nop + d.fsub.dd %f12,%f14,%f16 + nop + + d.fmul.ss %f11,%f12,%f13 + nop + d.fmul.sd %f14,%f15,%f16 + nop + d.fmul.dd %f18,%f20,%f22 + nop + + d.fmlow.dd %f8,%f10,%f12 + nop + + # Pipelined, with dual bit + d.pfadd.ss %f14,%f15,%f16 + nop + d.pfadd.sd %f17,%f18,%f20 + nop + d.pfadd.dd %f22,%f24,%f26 + nop + + d.pfsub.ss %f20,%f21,%f22 + nop + d.pfsub.sd %f23,%f24,%f26 + nop + d.pfsub.dd %f28,%f30,%f2 + nop + + d.pfmul.ss %f27,%f28,%f29 + nop + d.pfmul.sd %f30,%f31,%f4 + nop + d.pfmul.dd %f6,%f0,%f8 + nop + + d.pfmul3.dd %f2,%f4,%f30 + nop + diff --git a/gas/testsuite/gas/i860/float02.d b/gas/testsuite/gas/i860/float02.d new file mode 100644 index 00000000000..aae176ffec5 --- /dev/null +++ b/gas/testsuite/gas/i860/float02.d @@ -0,0 +1,39 @@ +#as: +#objdump: -dr +#name: i860 float02 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 22 00 01 48 frcp.ss %f0,%f1 + 4: a2 00 44 48 frcp.sd %f2,%f4 + 8: a2 01 c8 48 frcp.dd %f6,%f8 + c: 23 00 a6 48 frsqr.ss %f5,%f6 + 10: a3 00 0a 49 frsqr.sd %f8,%f10 + 14: a3 01 8e 49 frsqr.dd %f12,%f14 + 18: 33 08 1f 48 famov.ss %f1,%f31 + 1c: 33 11 1e 48 famov.ds %f2,%f30 + 20: b3 38 10 48 famov.sd %f7,%f16 + 24: b3 c1 0c 48 famov.dd %f24,%f12 + 28: 22 02 01 48 d.frcp.ss %f0,%f1 + 2c: 00 00 00 a0 shl %r0,%r0,%r0 + 30: a2 02 5e 48 d.frcp.sd %f2,%f30 + 34: 00 00 00 a0 shl %r0,%r0,%r0 + 38: a2 03 c8 48 d.frcp.dd %f6,%f8 + 3c: 00 00 00 a0 shl %r0,%r0,%r0 + 40: 23 02 a6 48 d.frsqr.ss %f5,%f6 + 44: 00 00 00 a0 shl %r0,%r0,%r0 + 48: a3 02 18 49 d.frsqr.sd %f8,%f24 + 4c: 00 00 00 a0 shl %r0,%r0,%r0 + 50: a3 03 8e 49 d.frsqr.dd %f12,%f14 + 54: 00 00 00 a0 shl %r0,%r0,%r0 + 58: 33 2a 0d 48 d.famov.ss %f5,%f13 + 5c: 00 00 00 a0 shl %r0,%r0,%r0 + 60: 33 f3 15 48 d.famov.ds %f30,%f21 + 64: 00 00 00 a0 shl %r0,%r0,%r0 + 68: b3 ba 16 48 d.famov.sd %f23,%f22 + 6c: 00 00 00 a0 shl %r0,%r0,%r0 + 70: b3 03 0c 48 d.famov.dd %f0,%f12 + 74: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/float02.s b/gas/testsuite/gas/i860/float02.s new file mode 100644 index 00000000000..d4a475d4102 --- /dev/null +++ b/gas/testsuite/gas/i860/float02.s @@ -0,0 +1,42 @@ +# frcp, frsqr, famov + + .text + + # Without dual bit + frcp.ss %f0,%f1 + frcp.sd %f2,%f4 + frcp.dd %f6,%f8 + + frsqr.ss %f5,%f6 + frsqr.sd %f8,%f10 + frsqr.dd %f12,%f14 + + famov.ss %f1,%f31 + famov.ds %f2,%f30 + famov.sd %f7,%f16 + famov.dd %f24,%f12 + + # With dual bit + d.frcp.ss %f0,%f1 + nop + d.frcp.sd %f2,%f30 + nop + d.frcp.dd %f6,%f8 + nop + + d.frsqr.ss %f5,%f6 + nop + d.frsqr.sd %f8,%f24 + nop + d.frsqr.dd %f12,%f14 + nop + + d.famov.ss %f5,%f13 + nop + d.famov.ds %f30,%f21 + nop + d.famov.sd %f23,%f22 + nop + d.famov.dd %f0,%f12 + nop + diff --git a/gas/testsuite/gas/i860/float03.d b/gas/testsuite/gas/i860/float03.d new file mode 100644 index 00000000000..10f66c23e4a --- /dev/null +++ b/gas/testsuite/gas/i860/float03.d @@ -0,0 +1,51 @@ +#as: +#objdump: -dr +#name: i860 float03 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: b2 10 04 48 fix.sd %f2,%f4 + 4: b2 31 08 48 fix.dd %f6,%f8 + 8: ba 40 0a 48 ftrunc.sd %f8,%f10 + c: ba 61 0e 48 ftrunc.dd %f12,%f14 + 10: b2 f4 0e 48 pfix.sd %f30,%f14 + 14: b2 c5 02 48 pfix.dd %f24,%f2 + 18: ba 44 0a 48 pftrunc.sd %f8,%f10 + 1c: ba 65 0e 48 pftrunc.dd %f12,%f14 + 20: 34 04 22 48 pfgt.ss %f0,%f1,%f2 + 24: 34 35 0a 49 pfgt.dd %f6,%f8,%f10 + 28: b4 2c c7 48 pfle.ss %f5,%f6,%f7 + 2c: b4 65 d0 49 pfle.dd %f12,%f14,%f16 + 30: 35 5c 8d 49 pfeq.ss %f11,%f12,%f13 + 34: 35 95 96 4a pfeq.dd %f18,%f20,%f22 + 38: b2 12 1e 48 d.fix.sd %f2,%f30 + 3c: 00 00 00 a0 shl %r0,%r0,%r0 + 40: b2 33 08 48 d.fix.dd %f6,%f8 + 44: 00 00 00 a0 shl %r0,%r0,%r0 + 48: ba 42 18 48 d.ftrunc.sd %f8,%f24 + 4c: 00 00 00 a0 shl %r0,%r0,%r0 + 50: ba 63 0e 48 d.ftrunc.dd %f12,%f14 + 54: 00 00 00 a0 shl %r0,%r0,%r0 + 58: b2 16 1e 48 d.pfix.sd %f2,%f30 + 5c: 00 00 00 a0 shl %r0,%r0,%r0 + 60: b2 37 08 48 d.pfix.dd %f6,%f8 + 64: 00 00 00 a0 shl %r0,%r0,%r0 + 68: ba 46 18 48 d.pftrunc.sd %f8,%f24 + 6c: 00 00 00 a0 shl %r0,%r0,%r0 + 70: ba 67 0e 48 d.pftrunc.dd %f12,%f14 + 74: 00 00 00 a0 shl %r0,%r0,%r0 + 78: 34 06 22 48 d.pfgt.ss %f0,%f1,%f2 + 7c: 00 00 00 a0 shl %r0,%r0,%r0 + 80: 34 37 0a 49 d.pfgt.dd %f6,%f8,%f10 + 84: 00 00 00 a0 shl %r0,%r0,%r0 + 88: b4 2e c7 48 d.pfle.ss %f5,%f6,%f7 + 8c: 00 00 00 a0 shl %r0,%r0,%r0 + 90: b4 67 d0 49 d.pfle.dd %f12,%f14,%f16 + 94: 00 00 00 a0 shl %r0,%r0,%r0 + 98: 35 5e 8d 49 d.pfeq.ss %f11,%f12,%f13 + 9c: 00 00 00 a0 shl %r0,%r0,%r0 + a0: 35 97 96 4a d.pfeq.dd %f18,%f20,%f22 + a4: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/float03.s b/gas/testsuite/gas/i860/float03.s new file mode 100644 index 00000000000..8fd626c4846 --- /dev/null +++ b/gas/testsuite/gas/i860/float03.s @@ -0,0 +1,64 @@ +# fix, ftrunc, pfgt, pfle, pfeq + + .text + + # Non-pipelined, without dual bit + fix.sd %f2,%f4 + fix.dd %f6,%f8 + + ftrunc.sd %f8,%f10 + ftrunc.dd %f12,%f14 + + # Pipelined, without dual bit + pfix.sd %f30,%f14 + pfix.dd %f24,%f2 + + pftrunc.sd %f8,%f10 + pftrunc.dd %f12,%f14 + + pfgt.ss %f0,%f1,%f2 + pfgt.dd %f6,%f8,%f10 + + pfle.ss %f5,%f6,%f7 + pfle.dd %f12,%f14,%f16 + + pfeq.ss %f11,%f12,%f13 + pfeq.dd %f18,%f20,%f22 + + # Non-pipelined, with dual bit + d.fix.sd %f2,%f30 + nop + d.fix.dd %f6,%f8 + nop + + d.ftrunc.sd %f8,%f24 + nop + d.ftrunc.dd %f12,%f14 + nop + + # Pipelined, with dual bit + d.pfix.sd %f2,%f30 + nop + d.pfix.dd %f6,%f8 + nop + + d.pftrunc.sd %f8,%f24 + nop + d.pftrunc.dd %f12,%f14 + nop + + d.pfgt.ss %f0,%f1,%f2 + nop + d.pfgt.dd %f6,%f8,%f10 + nop + + d.pfle.ss %f5,%f6,%f7 + nop + d.pfle.dd %f12,%f14,%f16 + nop + + d.pfeq.ss %f11,%f12,%f13 + nop + d.pfeq.dd %f18,%f20,%f22 + nop + diff --git a/gas/testsuite/gas/i860/float04.d b/gas/testsuite/gas/i860/float04.d new file mode 100644 index 00000000000..86406825a55 --- /dev/null +++ b/gas/testsuite/gas/i860/float04.d @@ -0,0 +1,39 @@ +#as: +#objdump: -dr +#name: i860 float04 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 40 08 03 48 fxfr %f1,%fp + 4: 40 40 1e 48 fxfr %f8,%r30 + 8: 40 f8 12 48 fxfr %f31,%r18 + c: 00 48 1f 08 ixfr %r9,%f31 + 10: 00 b8 10 08 ixfr %r23,%f16 + 14: 00 00 00 08 ixfr %r0,%f0 + 18: 49 00 22 48 fiadd.ss %f0,%f1,%f2 + 1c: c9 31 0a 49 fiadd.dd %f6,%f8,%f10 + 20: 4d 28 c7 48 fisub.ss %f5,%f6,%f7 + 24: cd 61 d0 49 fisub.dd %f12,%f14,%f16 + 28: 49 74 f0 49 pfiadd.ss %f14,%f15,%f16 + 2c: c9 b5 1a 4b pfiadd.dd %f22,%f24,%f26 + 30: 4d a4 b6 4a pfisub.ss %f20,%f21,%f22 + 34: cd e5 c2 4b pfisub.dd %f28,%f30,%f2 + 38: 49 02 22 48 d.fiadd.ss %f0,%f1,%f2 + 3c: 00 00 00 a0 shl %r0,%r0,%r0 + 40: c9 33 0a 49 d.fiadd.dd %f6,%f8,%f10 + 44: 00 00 00 a0 shl %r0,%r0,%r0 + 48: 4d 2a c7 48 d.fisub.ss %f5,%f6,%f7 + 4c: 00 00 00 a0 shl %r0,%r0,%r0 + 50: cd 63 d0 49 d.fisub.dd %f12,%f14,%f16 + 54: 00 00 00 a0 shl %r0,%r0,%r0 + 58: 49 76 f0 49 d.pfiadd.ss %f14,%f15,%f16 + 5c: 00 00 00 a0 shl %r0,%r0,%r0 + 60: c9 b7 1a 4b d.pfiadd.dd %f22,%f24,%f26 + 64: 00 00 00 a0 shl %r0,%r0,%r0 + 68: 4d a6 b6 4a d.pfisub.ss %f20,%f21,%f22 + 6c: 00 00 00 a0 shl %r0,%r0,%r0 + 70: cd e7 c2 4b d.pfisub.dd %f28,%f30,%f2 + 74: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/float04.s b/gas/testsuite/gas/i860/float04.s new file mode 100644 index 00000000000..5a4aae550bb --- /dev/null +++ b/gas/testsuite/gas/i860/float04.s @@ -0,0 +1,49 @@ +# fxfr, ixfr, fiadd, fisub + + .text + + # ixfr, fxfr + fxfr %f1,%r3 + fxfr %f8,%r30 + fxfr %f31,%r18 + + ixfr %r9,%f31 + ixfr %r23,%f16 + ixfr %r0,%f0 + + # Non-pipelined, without dual bit + fiadd.ss %f0,%f1,%f2 + fiadd.dd %f6,%f8,%f10 + + fisub.ss %f5,%f6,%f7 + fisub.dd %f12,%f14,%f16 + + # Pipelined, without dual bit + pfiadd.ss %f14,%f15,%f16 + pfiadd.dd %f22,%f24,%f26 + + pfisub.ss %f20,%f21,%f22 + pfisub.dd %f28,%f30,%f2 + + # Non-pipelined, with dual bit + d.fiadd.ss %f0,%f1,%f2 + nop + d.fiadd.dd %f6,%f8,%f10 + nop + + d.fisub.ss %f5,%f6,%f7 + nop + d.fisub.dd %f12,%f14,%f16 + nop + + # Pipelined, with dual bit + d.pfiadd.ss %f14,%f15,%f16 + nop + d.pfiadd.dd %f22,%f24,%f26 + nop + + d.pfisub.ss %f20,%f21,%f22 + nop + d.pfisub.dd %f28,%f30,%f2 + nop + diff --git a/gas/testsuite/gas/i860/form.d b/gas/testsuite/gas/i860/form.d new file mode 100644 index 00000000000..d713d8c0dab --- /dev/null +++ b/gas/testsuite/gas/i860/form.d @@ -0,0 +1,63 @@ +#as: +#objdump: -dr +#name: i860 form/pform + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: da 05 02 48 pform %f0,%f2 + 4: da 15 04 48 pform %f2,%f4 + 8: da 25 06 48 pform %f4,%f6 + c: da 45 0a 48 pform %f8,%f10 + 10: da 65 0e 48 pform %f12,%f14 + 14: da 85 12 48 pform %f16,%f18 + 18: da a5 16 48 pform %f20,%f22 + 1c: da c5 1a 48 pform %f24,%f26 + 20: da e5 1e 48 pform %f28,%f30 + 24: da 01 02 48 form %f0,%f2 + 28: da 11 04 48 form %f2,%f4 + 2c: da 21 06 48 form %f4,%f6 + 30: da 41 0a 48 form %f8,%f10 + 34: da 61 0e 48 form %f12,%f14 + 38: da 81 12 48 form %f16,%f18 + 3c: da a1 16 48 form %f20,%f22 + 40: da c1 1a 48 form %f24,%f26 + 44: da e1 1e 48 form %f28,%f30 + 48: da 07 02 48 d.pform %f0,%f2 + 4c: 00 00 00 a0 shl %r0,%r0,%r0 + 50: da 17 04 48 d.pform %f2,%f4 + 54: 00 00 00 a0 shl %r0,%r0,%r0 + 58: da 27 06 48 d.pform %f4,%f6 + 5c: 00 00 00 a0 shl %r0,%r0,%r0 + 60: da 47 0a 48 d.pform %f8,%f10 + 64: 00 00 00 a0 shl %r0,%r0,%r0 + 68: da 67 0e 48 d.pform %f12,%f14 + 6c: 00 00 00 a0 shl %r0,%r0,%r0 + 70: da 87 12 48 d.pform %f16,%f18 + 74: 00 00 00 a0 shl %r0,%r0,%r0 + 78: da a7 16 48 d.pform %f20,%f22 + 7c: 00 00 00 a0 shl %r0,%r0,%r0 + 80: da c7 1a 48 d.pform %f24,%f26 + 84: 00 00 00 a0 shl %r0,%r0,%r0 + 88: da e7 1e 48 d.pform %f28,%f30 + 8c: 00 00 00 a0 shl %r0,%r0,%r0 + 90: da 03 02 48 d.form %f0,%f2 + 94: 00 00 00 a0 shl %r0,%r0,%r0 + 98: da 13 04 48 d.form %f2,%f4 + 9c: 00 00 00 a0 shl %r0,%r0,%r0 + a0: da 23 06 48 d.form %f4,%f6 + a4: 00 00 00 a0 shl %r0,%r0,%r0 + a8: da 43 0a 48 d.form %f8,%f10 + ac: 00 00 00 a0 shl %r0,%r0,%r0 + b0: da 63 0e 48 d.form %f12,%f14 + b4: 00 00 00 a0 shl %r0,%r0,%r0 + b8: da 83 12 48 d.form %f16,%f18 + bc: 00 00 00 a0 shl %r0,%r0,%r0 + c0: da a3 16 48 d.form %f20,%f22 + c4: 00 00 00 a0 shl %r0,%r0,%r0 + c8: da c3 1a 48 d.form %f24,%f26 + cc: 00 00 00 a0 shl %r0,%r0,%r0 + d0: da e3 1e 48 d.form %f28,%f30 + d4: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/form.s b/gas/testsuite/gas/i860/form.s new file mode 100644 index 00000000000..e73dde6d336 --- /dev/null +++ b/gas/testsuite/gas/i860/form.s @@ -0,0 +1,66 @@ +# form and pform + + .text + + # pform, no dual bit + pform %f0,%f2 + pform %f2,%f4 + pform %f4,%f6 + pform %f8,%f10 + pform %f12,%f14 + pform %f16,%f18 + pform %f20,%f22 + pform %f24,%f26 + pform %f28,%f30 + + # form, no dual bit + form %f0,%f2 + form %f2,%f4 + form %f4,%f6 + form %f8,%f10 + form %f12,%f14 + form %f16,%f18 + form %f20,%f22 + form %f24,%f26 + form %f28,%f30 + + # pform, with dual bit + d.pform %f0,%f2 + nop + d.pform %f2,%f4 + nop + d.pform %f4,%f6 + nop + d.pform %f8,%f10 + nop + d.pform %f12,%f14 + nop + d.pform %f16,%f18 + nop + d.pform %f20,%f22 + nop + d.pform %f24,%f26 + nop + d.pform %f28,%f30 + nop + + # form, with dual bit + d.form %f0,%f2 + nop + d.form %f2,%f4 + nop + d.form %f4,%f6 + nop + d.form %f8,%f10 + nop + d.form %f12,%f14 + nop + d.form %f16,%f18 + nop + d.form %f20,%f22 + nop + d.form %f24,%f26 + nop + d.form %f28,%f30 + nop + diff --git a/gas/testsuite/gas/i860/i860.exp b/gas/testsuite/gas/i860/i860.exp new file mode 100644 index 00000000000..56dcc028aa0 --- /dev/null +++ b/gas/testsuite/gas/i860/i860.exp @@ -0,0 +1,63 @@ +# Copyright (C) 2012-2018 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +# i860 assembler testsuite. + +if [istarget i860-*-*] { + run_dump_test "bitwise" + run_dump_test "branch" + run_dump_test "bte" + run_dump_test "dir-align01" + run_dump_test "dir-intel01" + run_dump_test "dir-intel02" + run_list_test "dir-intel03-err" "" + run_dump_test "dual01" + run_list_test "dual02-err" "" + run_dump_test "dual03" + run_dump_test "fldst01" + run_dump_test "fldst02" + run_dump_test "fldst03" + run_dump_test "fldst04" + run_dump_test "fldst05" + run_dump_test "fldst06" + run_dump_test "fldst07" + run_dump_test "fldst08" + run_dump_test "float01" + run_dump_test "float02" + run_dump_test "float03" + run_dump_test "float04" + run_dump_test "form" + run_dump_test "iarith" + run_dump_test "ldst01" + run_dump_test "ldst02" + run_dump_test "ldst03" + run_dump_test "ldst04" + run_dump_test "ldst05" + run_dump_test "ldst06" + run_dump_test "pic" + run_dump_test "pfam" + run_dump_test "pfmam" + run_dump_test "pfmsm" + run_dump_test "pfsm" + run_dump_test "pseudo-ops01" + run_dump_test "regress01" + run_dump_test "shift" + run_dump_test "simd" + run_dump_test "system" + run_dump_test "xp" + gas_test "dual-frag.s" "" "" "dual mode alignment across frags" +} + diff --git a/gas/testsuite/gas/i860/iarith.d b/gas/testsuite/gas/i860/iarith.d new file mode 100644 index 00000000000..9b2a5095b52 --- /dev/null +++ b/gas/testsuite/gas/i860/iarith.d @@ -0,0 +1,97 @@ +#as: +#objdump: -dr +#name: i860 iarith + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 22 80 addu %r0,%r1,%sp + 4: 00 18 85 80 addu %fp,%r4,%r5 + 8: 00 30 e8 80 addu %r6,%r7,%r8 + c: 00 48 4b 81 addu %r9,%r10,%r11 + 10: 00 f8 ae 81 addu %r31,%r13,%r14 + 14: 00 78 11 82 addu %r15,%r16,%r17 + 18: 00 90 74 82 addu %r18,%r19,%r20 + 1c: 00 a8 d7 82 addu %r21,%r22,%r23 + 20: 00 c0 3f 83 addu %r24,%r25,%r31 + 24: 00 d8 9d 83 addu %r27,%r28,%r29 + 28: 00 f0 e0 83 addu %r30,%r31,%r0 + 2c: 00 00 22 90 adds %r0,%r1,%sp + 30: 00 18 85 90 adds %fp,%r4,%r5 + 34: 00 30 e8 90 adds %r6,%r7,%r8 + 38: 00 48 4b 91 adds %r9,%r10,%r11 + 3c: 00 f8 ae 91 adds %r31,%r13,%r14 + 40: 00 78 11 92 adds %r15,%r16,%r17 + 44: 00 90 74 92 adds %r18,%r19,%r20 + 48: 00 a8 d7 92 adds %r21,%r22,%r23 + 4c: 00 c0 3f 93 adds %r24,%r25,%r31 + 50: 00 d8 9d 93 adds %r27,%r28,%r29 + 54: 00 f0 e0 93 adds %r30,%r31,%r0 + 58: 00 00 22 88 subu %r0,%r1,%sp + 5c: 00 18 85 88 subu %fp,%r4,%r5 + 60: 00 30 e8 88 subu %r6,%r7,%r8 + 64: 00 48 4b 89 subu %r9,%r10,%r11 + 68: 00 f8 ae 89 subu %r31,%r13,%r14 + 6c: 00 78 11 8a subu %r15,%r16,%r17 + 70: 00 90 74 8a subu %r18,%r19,%r20 + 74: 00 a8 d7 8a subu %r21,%r22,%r23 + 78: 00 c0 3f 8b subu %r24,%r25,%r31 + 7c: 00 d8 9d 8b subu %r27,%r28,%r29 + 80: 00 f0 e0 8b subu %r30,%r31,%r0 + 84: 00 00 22 98 subs %r0,%r1,%sp + 88: 00 18 85 98 subs %fp,%r4,%r5 + 8c: 00 30 e8 98 subs %r6,%r7,%r8 + 90: 00 48 4b 99 subs %r9,%r10,%r11 + 94: 00 f8 ae 99 subs %r31,%r13,%r14 + 98: 00 78 11 9a subs %r15,%r16,%r17 + 9c: 00 90 74 9a subs %r18,%r19,%r20 + a0: 00 a8 d7 9a subs %r21,%r22,%r23 + a4: 00 c0 3f 9b subs %r24,%r25,%r31 + a8: 00 d8 9d 9b subs %r27,%r28,%r29 + ac: 00 f0 e0 9b subs %r30,%r31,%r0 + b0: 00 00 22 84 addu 0,%r1,%sp + b4: 00 20 85 84 addu 8192,%r4,%r5 + b8: f5 13 e8 84 addu 5109,%r7,%r8 + bc: ff 7f 4b 85 addu 32767,%r10,%r11 + c0: 00 80 ae 85 addu -32768,%r13,%r14 + c4: 00 e0 11 86 addu -8192,%r16,%r17 + c8: ff ff 74 86 addu -1,%r19,%r20 + cc: cd ab d7 86 addu -21555,%r22,%r23 + d0: 34 12 3a 87 addu 4660,%r25,%r26 + d4: 00 00 9d 87 addu 0,%r28,%r29 + d8: 03 00 e0 87 addu 3,%r31,%r0 + dc: 00 00 22 94 adds 0,%r1,%sp + e0: 00 20 85 94 adds 8192,%r4,%r5 + e4: f5 13 e8 94 adds 5109,%r7,%r8 + e8: ff 7f 4b 95 adds 32767,%r10,%r11 + ec: 00 80 ae 95 adds -32768,%r13,%r14 + f0: 00 e0 11 96 adds -8192,%r16,%r17 + f4: ff ff 74 96 adds -1,%r19,%r20 + f8: cd ab d7 96 adds -21555,%r22,%r23 + fc: 34 12 3a 97 adds 4660,%r25,%r26 + 100: 00 00 9d 97 adds 0,%r28,%r29 + 104: 03 00 e0 97 adds 3,%r31,%r0 + 108: 01 00 22 8c subu 1,%r1,%sp + 10c: 01 20 85 8c subu 8193,%r4,%r5 + 110: f6 13 e8 8c subu 5110,%r7,%r8 + 114: ff 7f 4b 8d subu 32767,%r10,%r11 + 118: 00 80 ae 8d subu -32768,%r13,%r14 + 11c: 00 e0 11 8e subu -8192,%r16,%r17 + 120: ff ff 74 8e subu -1,%r19,%r20 + 124: cd ab d7 8e subu -21555,%r22,%r23 + 128: 34 12 3a 8f subu 4660,%r25,%r26 + 12c: 00 00 9d 8f subu 0,%r28,%r29 + 130: 03 00 e0 8f subu 3,%r31,%r0 + 134: 01 00 22 9c subs 1,%r1,%sp + 138: 01 20 85 9c subs 8193,%r4,%r5 + 13c: f6 13 e8 9c subs 5110,%r7,%r8 + 140: ff 7f 4b 9d subs 32767,%r10,%r11 + 144: 00 80 ae 9d subs -32768,%r13,%r14 + 148: 00 e0 11 9e subs -8192,%r16,%r17 + 14c: ff ff 74 9e subs -1,%r19,%r20 + 150: cd ab d7 9e subs -21555,%r22,%r23 + 154: 34 12 3a 9f subs 4660,%r25,%r26 + 158: 00 00 9d 9f subs 0,%r28,%r29 + 15c: 03 00 e0 9f subs 3,%r31,%r0 diff --git a/gas/testsuite/gas/i860/iarith.s b/gas/testsuite/gas/i860/iarith.s new file mode 100644 index 00000000000..98a360e4efc --- /dev/null +++ b/gas/testsuite/gas/i860/iarith.s @@ -0,0 +1,102 @@ +# addu, adds, subu, subs + + .text + + # Register forms + addu %r0,%r1,%r2 + addu %r3,%r4,%r5 + addu %r6,%r7,%r8 + addu %r9,%r10,%r11 + addu %r31,%r13,%r14 + addu %r15,%r16,%r17 + addu %r18,%r19,%r20 + addu %r21,%r22,%r23 + addu %r24,%r25,%r31 + addu %r27,%r28,%r29 + addu %r30,%r31,%r0 + + adds %r0,%r1,%r2 + adds %r3,%r4,%r5 + adds %r6,%r7,%r8 + adds %r9,%r10,%r11 + adds %r31,%r13,%r14 + adds %r15,%r16,%r17 + adds %r18,%r19,%r20 + adds %r21,%r22,%r23 + adds %r24,%r25,%r31 + adds %r27,%r28,%r29 + adds %r30,%r31,%r0 + + subu %r0,%r1,%r2 + subu %r3,%r4,%r5 + subu %r6,%r7,%r8 + subu %r9,%r10,%r11 + subu %r31,%r13,%r14 + subu %r15,%r16,%r17 + subu %r18,%r19,%r20 + subu %r21,%r22,%r23 + subu %r24,%r25,%r31 + subu %r27,%r28,%r29 + subu %r30,%r31,%r0 + + subs %r0,%r1,%r2 + subs %r3,%r4,%r5 + subs %r6,%r7,%r8 + subs %r9,%r10,%r11 + subs %r31,%r13,%r14 + subs %r15,%r16,%r17 + subs %r18,%r19,%r20 + subs %r21,%r22,%r23 + subs %r24,%r25,%r31 + subs %r27,%r28,%r29 + subs %r30,%r31,%r0 + + # Immediate forms (all) + addu 0,%r1,%r2 + addu 8192,%r4,%r5 + addu 5109,%r7,%r8 + addu 32767,%r10,%r11 + addu -32768,%r13,%r14 + addu -8192,%r16,%r17 + addu -1,%r19,%r20 + addu -21555,%r22,%r23 + addu 0x1234,%r25,%r26 + addu 0x0,%r28,%r29 + addu 0x3,%r31,%r0 + + adds 0,%r1,%r2 + adds 8192,%r4,%r5 + adds 5109,%r7,%r8 + adds 32767,%r10,%r11 + adds -32768,%r13,%r14 + adds -8192,%r16,%r17 + adds -1,%r19,%r20 + adds -21555,%r22,%r23 + adds 0x1234,%r25,%r26 + adds 0x0,%r28,%r29 + adds 0x3,%r31,%r0 + + subu 1,%r1,%r2 + subu 8193,%r4,%r5 + subu 5110,%r7,%r8 + subu 32767,%r10,%r11 + subu -32768,%r13,%r14 + subu -8192,%r16,%r17 + subu -1,%r19,%r20 + subu -21555,%r22,%r23 + subu 0x1234,%r25,%r26 + subu 0x0,%r28,%r29 + subu 0x3,%r31,%r0 + + subs 1,%r1,%r2 + subs 8193,%r4,%r5 + subs 5110,%r7,%r8 + subs 32767,%r10,%r11 + subs -32768,%r13,%r14 + subs -8192,%r16,%r17 + subs -1,%r19,%r20 + subs -21555,%r22,%r23 + subs 0x1234,%r25,%r26 + subs 0x0,%r28,%r29 + subs 0x3,%r31,%r0 + diff --git a/gas/testsuite/gas/i860/ldst01.d b/gas/testsuite/gas/i860/ldst01.d new file mode 100644 index 00000000000..6c1330bf73f --- /dev/null +++ b/gas/testsuite/gas/i860/ldst01.d @@ -0,0 +1,39 @@ +#as: +#objdump: -dr +#name: i860 ldst01 (ld.l) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 01 00 00 14 ld.l 0\(%r0\),%r0 + 4: 7d 00 3f 14 ld.l 124\(%r1\),%r31 + 8: 01 01 5e 14 ld.l 256\(%sp\),%r30 + c: 01 02 7d 14 ld.l 512\(%fp\),%r29 + 10: 01 04 9c 14 ld.l 1024\(%r4\),%r28 + 14: 01 10 bb 14 ld.l 4096\(%r5\),%r27 + 18: 01 20 da 14 ld.l 8192\(%r6\),%r26 + 1c: 01 40 f9 14 ld.l 16384\(%r7\),%r25 + 20: 01 c0 18 15 ld.l -16384\(%r8\),%r24 + 24: 01 e0 37 15 ld.l -8192\(%r9\),%r23 + 28: 01 f0 56 15 ld.l -4096\(%r10\),%r22 + 2c: 01 fc 75 15 ld.l -1024\(%r11\),%r21 + 30: 05 fe 94 15 ld.l -508\(%r12\),%r20 + 34: 09 ff b3 15 ld.l -248\(%r13\),%r19 + 38: fd ff d2 15 ld.l -4\(%r14\),%r18 + 3c: 01 28 00 10 ld.l %r5\(%r0\),%r0 + 40: 01 30 3f 10 ld.l %r6\(%r1\),%r31 + 44: 01 38 5e 10 ld.l %r7\(%sp\),%r30 + 48: 01 40 7d 10 ld.l %r8\(%fp\),%r29 + 4c: 01 48 9c 10 ld.l %r9\(%r4\),%r28 + 50: 01 00 bb 10 ld.l %r0\(%r5\),%r27 + 54: 01 08 da 10 ld.l %r1\(%r6\),%r26 + 58: 01 60 f9 10 ld.l %r12\(%r7\),%r25 + 5c: 01 68 18 11 ld.l %r13\(%r8\),%r24 + 60: 01 70 37 11 ld.l %r14\(%r9\),%r23 + 64: 01 78 56 11 ld.l %r15\(%r10\),%r22 + 68: 01 80 75 11 ld.l %r16\(%r11\),%r21 + 6c: 01 88 94 11 ld.l %r17\(%r12\),%r20 + 70: 01 e0 b3 11 ld.l %r28\(%r13\),%r19 + 74: 01 f8 d2 11 ld.l %r31\(%r14\),%r18 diff --git a/gas/testsuite/gas/i860/ldst01.s b/gas/testsuite/gas/i860/ldst01.s new file mode 100644 index 00000000000..498f3469d36 --- /dev/null +++ b/gas/testsuite/gas/i860/ldst01.s @@ -0,0 +1,35 @@ +# ld.l (no relocations here) + .text + + ld.l 0(%r0),%r0 + ld.l 124(%r1),%r31 + ld.l 256(%r2),%r30 + ld.l 512(%r3),%r29 + ld.l 1024(%r4),%r28 + ld.l 4096(%r5),%r27 + ld.l 8192(%r6),%r26 + ld.l 16384(%r7),%r25 + ld.l -16384(%r8),%r24 + ld.l -8192(%r9),%r23 + ld.l -4096(%r10),%r22 + ld.l -1024(%r11),%r21 + ld.l -508(%r12),%r20 + ld.l -248(%r13),%r19 + ld.l -4(%r14),%r18 + + ld.l %r5(%r0),%r0 + ld.l %r6(%r1),%r31 + ld.l %r7(%r2),%r30 + ld.l %r8(%r3),%r29 + ld.l %r9(%r4),%r28 + ld.l %r0(%r5),%r27 + ld.l %r1(%r6),%r26 + ld.l %r12(%r7),%r25 + ld.l %r13(%r8),%r24 + ld.l %r14(%r9),%r23 + ld.l %r15(%r10),%r22 + ld.l %r16(%r11),%r21 + ld.l %r17(%r12),%r20 + ld.l %r28(%r13),%r19 + ld.l %r31(%r14),%r18 + diff --git a/gas/testsuite/gas/i860/ldst02.d b/gas/testsuite/gas/i860/ldst02.d new file mode 100644 index 00000000000..ec03ae515ed --- /dev/null +++ b/gas/testsuite/gas/i860/ldst02.d @@ -0,0 +1,39 @@ +#as: +#objdump: -dr +#name: i860 ldst02 (ld.s) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 14 ld.s 0\(%r0\),%r0 + 4: 7a 00 3f 14 ld.s 122\(%r1\),%r31 + 8: 02 01 5e 14 ld.s 258\(%sp\),%r30 + c: 00 02 7d 14 ld.s 512\(%fp\),%r29 + 10: 04 04 9c 14 ld.s 1028\(%r4\),%r28 + 14: fa 0f bb 14 ld.s 4090\(%r5\),%r27 + 18: fe 1f da 14 ld.s 8190\(%r6\),%r26 + 1c: 00 40 f9 14 ld.s 16384\(%r7\),%r25 + 20: 00 c0 18 15 ld.s -16384\(%r8\),%r24 + 24: 00 e0 37 15 ld.s -8192\(%r9\),%r23 + 28: 00 f0 56 15 ld.s -4096\(%r10\),%r22 + 2c: 00 fc 75 15 ld.s -1024\(%r11\),%r21 + 30: 04 fe 94 15 ld.s -508\(%r12\),%r20 + 34: 0e ff b3 15 ld.s -242\(%r13\),%r19 + 38: fe ff d2 15 ld.s -2\(%r14\),%r18 + 3c: 00 28 00 10 ld.s %r5\(%r0\),%r0 + 40: 00 30 3f 10 ld.s %r6\(%r1\),%r31 + 44: 00 38 5e 10 ld.s %r7\(%sp\),%r30 + 48: 00 40 7d 10 ld.s %r8\(%fp\),%r29 + 4c: 00 48 9c 10 ld.s %r9\(%r4\),%r28 + 50: 00 00 bb 10 ld.s %r0\(%r5\),%r27 + 54: 00 08 da 10 ld.s %r1\(%r6\),%r26 + 58: 00 60 f9 10 ld.s %r12\(%r7\),%r25 + 5c: 00 68 18 11 ld.s %r13\(%r8\),%r24 + 60: 00 70 37 11 ld.s %r14\(%r9\),%r23 + 64: 00 78 56 11 ld.s %r15\(%r10\),%r22 + 68: 00 80 75 11 ld.s %r16\(%r11\),%r21 + 6c: 00 88 94 11 ld.s %r17\(%r12\),%r20 + 70: 00 e0 b3 11 ld.s %r28\(%r13\),%r19 + 74: 00 f8 d2 11 ld.s %r31\(%r14\),%r18 diff --git a/gas/testsuite/gas/i860/ldst02.s b/gas/testsuite/gas/i860/ldst02.s new file mode 100644 index 00000000000..52c0e1ab370 --- /dev/null +++ b/gas/testsuite/gas/i860/ldst02.s @@ -0,0 +1,35 @@ +# ld.s (no relocations here) + .text + + ld.s 0(%r0),%r0 + ld.s 122(%r1),%r31 + ld.s 258(%r2),%r30 + ld.s 512(%r3),%r29 + ld.s 1028(%r4),%r28 + ld.s 4090(%r5),%r27 + ld.s 8190(%r6),%r26 + ld.s 16384(%r7),%r25 + ld.s -16384(%r8),%r24 + ld.s -8192(%r9),%r23 + ld.s -4096(%r10),%r22 + ld.s -1024(%r11),%r21 + ld.s -508(%r12),%r20 + ld.s -242(%r13),%r19 + ld.s -2(%r14),%r18 + + ld.s %r5(%r0),%r0 + ld.s %r6(%r1),%r31 + ld.s %r7(%r2),%r30 + ld.s %r8(%r3),%r29 + ld.s %r9(%r4),%r28 + ld.s %r0(%r5),%r27 + ld.s %r1(%r6),%r26 + ld.s %r12(%r7),%r25 + ld.s %r13(%r8),%r24 + ld.s %r14(%r9),%r23 + ld.s %r15(%r10),%r22 + ld.s %r16(%r11),%r21 + ld.s %r17(%r12),%r20 + ld.s %r28(%r13),%r19 + ld.s %r31(%r14),%r18 + diff --git a/gas/testsuite/gas/i860/ldst03.d b/gas/testsuite/gas/i860/ldst03.d new file mode 100644 index 00000000000..f3f0008f61c --- /dev/null +++ b/gas/testsuite/gas/i860/ldst03.d @@ -0,0 +1,43 @@ +#as: +#objdump: -dr +#name: i860 ldst03 (ld.b) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 04 ld.b 0\(%r0\),%r0 + 4: 01 00 3f 04 ld.b 1\(%r1\),%r31 + 8: 02 00 5e 04 ld.b 2\(%sp\),%r30 + c: 01 02 7d 04 ld.b 513\(%fp\),%r29 + 10: 04 04 9c 04 ld.b 1028\(%r4\),%r28 + 14: fa 0f bb 04 ld.b 4090\(%r5\),%r27 + 18: fe 1f da 04 ld.b 8190\(%r6\),%r26 + 1c: 01 40 f9 04 ld.b 16385\(%r7\),%r25 + 20: 07 7d f9 04 ld.b 32007\(%r7\),%r25 + 24: ff 7f f9 04 ld.b 32767\(%r7\),%r25 + 28: 00 80 f9 04 ld.b -32768\(%r7\),%r25 + 2c: 01 80 f9 04 ld.b -32767\(%r7\),%r25 + 30: 01 c0 18 05 ld.b -16383\(%r8\),%r24 + 34: 5b e0 37 05 ld.b -8101\(%r9\),%r23 + 38: 05 f0 56 05 ld.b -4091\(%r10\),%r22 + 3c: 01 fc 75 05 ld.b -1023\(%r11\),%r21 + 40: 03 fe 94 05 ld.b -509\(%r12\),%r20 + 44: e9 ff b3 05 ld.b -23\(%r13\),%r19 + 48: ff ff d2 05 ld.b -1\(%r14\),%r18 + 4c: 00 28 00 00 ld.b %r5\(%r0\),%r0 + 50: 00 30 3f 00 ld.b %r6\(%r1\),%r31 + 54: 00 38 5e 00 ld.b %r7\(%sp\),%r30 + 58: 00 40 7d 00 ld.b %r8\(%fp\),%r29 + 5c: 00 48 9c 00 ld.b %r9\(%r4\),%r28 + 60: 00 00 bb 00 ld.b %r0\(%r5\),%r27 + 64: 00 08 da 00 ld.b %r1\(%r6\),%r26 + 68: 00 60 f9 00 ld.b %r12\(%r7\),%r25 + 6c: 00 68 18 01 ld.b %r13\(%r8\),%r24 + 70: 00 70 37 01 ld.b %r14\(%r9\),%r23 + 74: 00 78 56 01 ld.b %r15\(%r10\),%r22 + 78: 00 80 75 01 ld.b %r16\(%r11\),%r21 + 7c: 00 88 94 01 ld.b %r17\(%r12\),%r20 + 80: 00 e0 b3 01 ld.b %r28\(%r13\),%r19 + 84: 00 f8 d2 01 ld.b %r31\(%r14\),%r18 diff --git a/gas/testsuite/gas/i860/ldst03.s b/gas/testsuite/gas/i860/ldst03.s new file mode 100644 index 00000000000..055a3b8c1a2 --- /dev/null +++ b/gas/testsuite/gas/i860/ldst03.s @@ -0,0 +1,39 @@ +# ld.b (no relocations here) + .text + + ld.b 0(%r0),%r0 + ld.b 1(%r1),%r31 + ld.b 2(%r2),%r30 + ld.b 513(%r3),%r29 + ld.b 1028(%r4),%r28 + ld.b 4090(%r5),%r27 + ld.b 8190(%r6),%r26 + ld.b 16385(%r7),%r25 + ld.b 32007(%r7),%r25 + ld.b 32767(%r7),%r25 + ld.b -32768(%r7),%r25 + ld.b -32767(%r7),%r25 + ld.b -16383(%r8),%r24 + ld.b -8101(%r9),%r23 + ld.b -4091(%r10),%r22 + ld.b -1023(%r11),%r21 + ld.b -509(%r12),%r20 + ld.b -23(%r13),%r19 + ld.b -1(%r14),%r18 + + ld.b %r5(%r0),%r0 + ld.b %r6(%r1),%r31 + ld.b %r7(%r2),%r30 + ld.b %r8(%r3),%r29 + ld.b %r9(%r4),%r28 + ld.b %r0(%r5),%r27 + ld.b %r1(%r6),%r26 + ld.b %r12(%r7),%r25 + ld.b %r13(%r8),%r24 + ld.b %r14(%r9),%r23 + ld.b %r15(%r10),%r22 + ld.b %r16(%r11),%r21 + ld.b %r17(%r12),%r20 + ld.b %r28(%r13),%r19 + ld.b %r31(%r14),%r18 + diff --git a/gas/testsuite/gas/i860/ldst04.d b/gas/testsuite/gas/i860/ldst04.d new file mode 100644 index 00000000000..a9130ac0221 --- /dev/null +++ b/gas/testsuite/gas/i860/ldst04.d @@ -0,0 +1,24 @@ +#as: +#objdump: -dr +#name: i860 ldst04 (st.l) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 01 00 00 1c st.l %r0,0\(%r0\) + 4: 7d f8 20 1c st.l %r31,124\(%r1\) + 8: 01 f1 40 1c st.l %r30,256\(%sp\) + c: 01 ea 60 1c st.l %r29,512\(%fp\) + 10: 01 e4 80 1c st.l %r28,1024\(%r4\) + 14: 01 d8 a2 1c st.l %r27,4096\(%r5\) + 18: 01 d0 c4 1c st.l %r26,8192\(%r6\) + 1c: 01 c8 e8 1c st.l %r25,16384\(%r7\) + 20: 01 c0 18 1d st.l %r24,-16384\(%r8\) + 24: 01 b8 3c 1d st.l %r23,-8192\(%r9\) + 28: 01 b0 5e 1d st.l %r22,-4096\(%r10\) + 2c: 01 ac 7f 1d st.l %r21,-1024\(%r11\) + 30: 05 a6 9f 1d st.l %r20,-508\(%r12\) + 34: 09 9f bf 1d st.l %r19,-248\(%r13\) + 38: fd 97 df 1d st.l %r18,-4\(%r14\) diff --git a/gas/testsuite/gas/i860/ldst04.s b/gas/testsuite/gas/i860/ldst04.s new file mode 100644 index 00000000000..8e22b6fe781 --- /dev/null +++ b/gas/testsuite/gas/i860/ldst04.s @@ -0,0 +1,19 @@ +# st.l (no relocations here) + .text + + st.l %r0,0(%r0) + st.l %r31,124(%r1) + st.l %r30,256(%r2) + st.l %r29,512(%r3) + st.l %r28,1024(%r4) + st.l %r27,4096(%r5) + st.l %r26,8192(%r6) + st.l %r25,16384(%r7) + st.l %r24,-16384(%r8) + st.l %r23,-8192(%r9) + st.l %r22,-4096(%r10) + st.l %r21,-1024(%r11) + st.l %r20,-508(%r12) + st.l %r19,-248(%r13) + st.l %r18,-4(%r14) + diff --git a/gas/testsuite/gas/i860/ldst05.d b/gas/testsuite/gas/i860/ldst05.d new file mode 100644 index 00000000000..e57f8227dd3 --- /dev/null +++ b/gas/testsuite/gas/i860/ldst05.d @@ -0,0 +1,24 @@ +#as: +#objdump: -dr +#name: i860 ldst05 (st.s) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 1c st.s %r0,0\(%r0\) + 4: 7a f8 20 1c st.s %r31,122\(%r1\) + 8: 02 f1 40 1c st.s %r30,258\(%sp\) + c: 00 ea 60 1c st.s %r29,512\(%fp\) + 10: 04 e4 80 1c st.s %r28,1028\(%r4\) + 14: fa df a1 1c st.s %r27,4090\(%r5\) + 18: fe d7 c3 1c st.s %r26,8190\(%r6\) + 1c: 00 c8 e8 1c st.s %r25,16384\(%r7\) + 20: 00 c0 18 1d st.s %r24,-16384\(%r8\) + 24: 00 b8 3c 1d st.s %r23,-8192\(%r9\) + 28: 00 b0 5e 1d st.s %r22,-4096\(%r10\) + 2c: 00 ac 7f 1d st.s %r21,-1024\(%r11\) + 30: 04 a6 9f 1d st.s %r20,-508\(%r12\) + 34: 0e 9f bf 1d st.s %r19,-242\(%r13\) + 38: fe 97 df 1d st.s %r18,-2\(%r14\) diff --git a/gas/testsuite/gas/i860/ldst05.s b/gas/testsuite/gas/i860/ldst05.s new file mode 100644 index 00000000000..7f253f492d1 --- /dev/null +++ b/gas/testsuite/gas/i860/ldst05.s @@ -0,0 +1,19 @@ +# st.s (no relocations here) + .text + + st.s %r0,0(%r0) + st.s %r31,122(%r1) + st.s %r30,258(%r2) + st.s %r29,512(%r3) + st.s %r28,1028(%r4) + st.s %r27,4090(%r5) + st.s %r26,8190(%r6) + st.s %r25,16384(%r7) + st.s %r24,-16384(%r8) + st.s %r23,-8192(%r9) + st.s %r22,-4096(%r10) + st.s %r21,-1024(%r11) + st.s %r20,-508(%r12) + st.s %r19,-242(%r13) + st.s %r18,-2(%r14) + diff --git a/gas/testsuite/gas/i860/ldst06.d b/gas/testsuite/gas/i860/ldst06.d new file mode 100644 index 00000000000..a1c54d185aa --- /dev/null +++ b/gas/testsuite/gas/i860/ldst06.d @@ -0,0 +1,28 @@ +#as: +#objdump: -dr +#name: i860 ldst06 (st.b) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 00 0c st.b %r0,0\(%r0\) + 4: 01 f8 20 0c st.b %r31,1\(%r1\) + 8: 02 f0 40 0c st.b %r30,2\(%sp\) + c: 01 ea 60 0c st.b %r29,513\(%fp\) + 10: 04 e4 80 0c st.b %r28,1028\(%r4\) + 14: fa df a1 0c st.b %r27,4090\(%r5\) + 18: fe d7 c3 0c st.b %r26,8190\(%r6\) + 1c: 01 c8 e8 0c st.b %r25,16385\(%r7\) + 20: 07 cd ef 0c st.b %r25,32007\(%r7\) + 24: ff cf ef 0c st.b %r25,32767\(%r7\) + 28: 00 c8 f0 0c st.b %r25,-32768\(%r7\) + 2c: 01 c8 f0 0c st.b %r25,-32767\(%r7\) + 30: 01 c0 18 0d st.b %r24,-16383\(%r8\) + 34: 5b b8 3c 0d st.b %r23,-8101\(%r9\) + 38: 05 b0 5e 0d st.b %r22,-4091\(%r10\) + 3c: 01 ac 7f 0d st.b %r21,-1023\(%r11\) + 40: 03 a6 9f 0d st.b %r20,-509\(%r12\) + 44: e9 9f bf 0d st.b %r19,-23\(%r13\) + 48: ff 97 df 0d st.b %r18,-1\(%r14\) diff --git a/gas/testsuite/gas/i860/ldst06.s b/gas/testsuite/gas/i860/ldst06.s new file mode 100644 index 00000000000..bb817ab736f --- /dev/null +++ b/gas/testsuite/gas/i860/ldst06.s @@ -0,0 +1,22 @@ +# st.b (no relocations here) + .text + + st.b %r0,0(%r0) + st.b %r31,1(%r1) + st.b %r30,2(%r2) + st.b %r29,513(%r3) + st.b %r28,1028(%r4) + st.b %r27,4090(%r5) + st.b %r26,8190(%r6) + st.b %r25,16385(%r7) + st.b %r25,32007(%r7) + st.b %r25,32767(%r7) + st.b %r25,-32768(%r7) + st.b %r25,-32767(%r7) + st.b %r24,-16383(%r8) + st.b %r23,-8101(%r9) + st.b %r22,-4091(%r10) + st.b %r21,-1023(%r11) + st.b %r20,-509(%r12) + st.b %r19,-23(%r13) + st.b %r18,-1(%r14) diff --git a/gas/testsuite/gas/i860/pfam.d b/gas/testsuite/gas/i860/pfam.d new file mode 100644 index 00000000000..2d95081b1ff --- /dev/null +++ b/gas/testsuite/gas/i860/pfam.d @@ -0,0 +1,153 @@ +#as: +#objdump: -dr +#name: i860 pfam + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 04 22 48 r2p1.ss %f0,%f1,%f2 + 4: 80 1c 85 48 r2p1.sd %f3,%f4,%f5 + 8: 80 05 44 48 r2p1.dd %f0,%f2,%f4 + c: 01 0c 43 48 r2pt.ss %f1,%f2,%f3 + 10: 81 24 a6 48 r2pt.sd %f4,%f5,%f6 + 14: 81 15 86 48 r2pt.dd %f2,%f4,%f6 + 18: 02 14 64 48 r2ap1.ss %f2,%f3,%f4 + 1c: 82 34 e8 48 r2ap1.sd %f6,%f7,%f8 + 20: 82 25 c8 48 r2ap1.dd %f4,%f6,%f8 + 24: 03 1c 85 48 r2apt.ss %f3,%f4,%f5 + 28: 83 3c 09 49 r2apt.sd %f7,%f8,%f9 + 2c: 83 35 0a 49 r2apt.dd %f6,%f8,%f10 + 30: 04 24 a6 48 i2p1.ss %f4,%f5,%f6 + 34: 84 44 2a 49 i2p1.sd %f8,%f9,%f10 + 38: 84 65 d0 49 i2p1.dd %f12,%f14,%f16 + 3c: 05 3c 09 49 i2pt.ss %f7,%f8,%f9 + 40: 85 5c 8d 49 i2pt.sd %f11,%f12,%f13 + 44: 85 75 12 4a i2pt.dd %f14,%f16,%f18 + 48: 06 54 6c 49 i2ap1.ss %f10,%f11,%f12 + 4c: 86 74 f0 49 i2ap1.sd %f14,%f15,%f16 + 50: 86 85 54 4a i2ap1.dd %f16,%f18,%f20 + 54: 07 6c cf 49 i2apt.ss %f13,%f14,%f15 + 58: 87 8c 53 4a i2apt.sd %f17,%f18,%f19 + 5c: 87 95 96 4a i2apt.dd %f18,%f20,%f22 + 60: 08 74 f0 49 rat1p2.ss %f14,%f15,%f16 + 64: 88 a4 b6 4a rat1p2.sd %f20,%f21,%f22 + 68: 88 a5 d8 4a rat1p2.dd %f20,%f22,%f24 + 6c: 09 7c 11 4a m12apm.ss %f15,%f16,%f17 + 70: 89 bc 19 4b m12apm.sd %f23,%f24,%f25 + 74: 89 b5 1a 4b m12apm.dd %f22,%f24,%f26 + 78: 0a 94 74 4a ra1p2.ss %f18,%f19,%f20 + 7c: 8a d4 7c 4b ra1p2.sd %f26,%f27,%f28 + 80: 8a a5 d8 4a ra1p2.dd %f20,%f22,%f24 + 84: 0b 9c 95 4a m12ttpa.ss %f19,%f20,%f21 + 88: 8b ec df 4b m12ttpa.sd %f29,%f30,%f31 + 8c: 8b b5 1a 4b m12ttpa.dd %f22,%f24,%f26 + 90: 0c a4 b6 4a iat1p2.ss %f20,%f21,%f22 + 94: 8c 04 22 48 iat1p2.sd %f0,%f1,%f2 + 98: 8c c5 5c 4b iat1p2.dd %f24,%f26,%f28 + 9c: 0d ac d7 4a m12tpm.ss %f21,%f22,%f23 + a0: 8d 1c 85 48 m12tpm.sd %f3,%f4,%f5 + a4: 8d f5 02 48 m12tpm.dd %f30,%f0,%f2 + a8: 0e b4 f8 4a ia1p2.ss %f22,%f23,%f24 + ac: 8e 34 e8 48 ia1p2.sd %f6,%f7,%f8 + b0: 8e 25 c8 48 ia1p2.dd %f4,%f6,%f8 + b4: 0f bc 19 4b m12tpa.ss %f23,%f24,%f25 + b8: 8f 4c 4b 49 m12tpa.sd %f9,%f10,%f11 + bc: 8f 35 0a 49 m12tpa.dd %f6,%f8,%f10 + c0: 00 06 22 48 d.r2p1.ss %f0,%f1,%f2 + c4: 00 00 00 a0 shl %r0,%r0,%r0 + c8: 80 1e 85 48 d.r2p1.sd %f3,%f4,%f5 + cc: 00 00 00 a0 shl %r0,%r0,%r0 + d0: 80 07 44 48 d.r2p1.dd %f0,%f2,%f4 + d4: 00 00 00 a0 shl %r0,%r0,%r0 + d8: 01 0e 43 48 d.r2pt.ss %f1,%f2,%f3 + dc: 00 00 00 a0 shl %r0,%r0,%r0 + e0: 81 26 a6 48 d.r2pt.sd %f4,%f5,%f6 + e4: 00 00 00 a0 shl %r0,%r0,%r0 + e8: 81 17 86 48 d.r2pt.dd %f2,%f4,%f6 + ec: 00 00 00 a0 shl %r0,%r0,%r0 + f0: 02 16 64 48 d.r2ap1.ss %f2,%f3,%f4 + f4: 00 00 00 a0 shl %r0,%r0,%r0 + f8: 82 36 e8 48 d.r2ap1.sd %f6,%f7,%f8 + fc: 00 00 00 a0 shl %r0,%r0,%r0 + 100: 82 27 c8 48 d.r2ap1.dd %f4,%f6,%f8 + 104: 00 00 00 a0 shl %r0,%r0,%r0 + 108: 03 1e 85 48 d.r2apt.ss %f3,%f4,%f5 + 10c: 00 00 00 a0 shl %r0,%r0,%r0 + 110: 83 3e 09 49 d.r2apt.sd %f7,%f8,%f9 + 114: 00 00 00 a0 shl %r0,%r0,%r0 + 118: 83 37 0a 49 d.r2apt.dd %f6,%f8,%f10 + 11c: 00 00 00 a0 shl %r0,%r0,%r0 + 120: 04 26 a6 48 d.i2p1.ss %f4,%f5,%f6 + 124: 00 00 00 a0 shl %r0,%r0,%r0 + 128: 84 46 2a 49 d.i2p1.sd %f8,%f9,%f10 + 12c: 00 00 00 a0 shl %r0,%r0,%r0 + 130: 84 67 d0 49 d.i2p1.dd %f12,%f14,%f16 + 134: 00 00 00 a0 shl %r0,%r0,%r0 + 138: 05 3e 09 49 d.i2pt.ss %f7,%f8,%f9 + 13c: 00 00 00 a0 shl %r0,%r0,%r0 + 140: 85 5e 8d 49 d.i2pt.sd %f11,%f12,%f13 + 144: 00 00 00 a0 shl %r0,%r0,%r0 + 148: 85 77 12 4a d.i2pt.dd %f14,%f16,%f18 + 14c: 00 00 00 a0 shl %r0,%r0,%r0 + 150: 06 56 6c 49 d.i2ap1.ss %f10,%f11,%f12 + 154: 00 00 00 a0 shl %r0,%r0,%r0 + 158: 86 76 f0 49 d.i2ap1.sd %f14,%f15,%f16 + 15c: 00 00 00 a0 shl %r0,%r0,%r0 + 160: 86 87 54 4a d.i2ap1.dd %f16,%f18,%f20 + 164: 00 00 00 a0 shl %r0,%r0,%r0 + 168: 07 6e cf 49 d.i2apt.ss %f13,%f14,%f15 + 16c: 00 00 00 a0 shl %r0,%r0,%r0 + 170: 87 8e 53 4a d.i2apt.sd %f17,%f18,%f19 + 174: 00 00 00 a0 shl %r0,%r0,%r0 + 178: 87 97 96 4a d.i2apt.dd %f18,%f20,%f22 + 17c: 00 00 00 a0 shl %r0,%r0,%r0 + 180: 08 76 f0 49 d.rat1p2.ss %f14,%f15,%f16 + 184: 00 00 00 a0 shl %r0,%r0,%r0 + 188: 88 a6 b6 4a d.rat1p2.sd %f20,%f21,%f22 + 18c: 00 00 00 a0 shl %r0,%r0,%r0 + 190: 88 a7 d8 4a d.rat1p2.dd %f20,%f22,%f24 + 194: 00 00 00 a0 shl %r0,%r0,%r0 + 198: 09 7e 11 4a d.m12apm.ss %f15,%f16,%f17 + 19c: 00 00 00 a0 shl %r0,%r0,%r0 + 1a0: 89 be 19 4b d.m12apm.sd %f23,%f24,%f25 + 1a4: 00 00 00 a0 shl %r0,%r0,%r0 + 1a8: 89 b7 1a 4b d.m12apm.dd %f22,%f24,%f26 + 1ac: 00 00 00 a0 shl %r0,%r0,%r0 + 1b0: 0a 96 74 4a d.ra1p2.ss %f18,%f19,%f20 + 1b4: 00 00 00 a0 shl %r0,%r0,%r0 + 1b8: 8a d6 7c 4b d.ra1p2.sd %f26,%f27,%f28 + 1bc: 00 00 00 a0 shl %r0,%r0,%r0 + 1c0: 8a a7 d8 4a d.ra1p2.dd %f20,%f22,%f24 + 1c4: 00 00 00 a0 shl %r0,%r0,%r0 + 1c8: 0b 9e 95 4a d.m12ttpa.ss %f19,%f20,%f21 + 1cc: 00 00 00 a0 shl %r0,%r0,%r0 + 1d0: 8b ee df 4b d.m12ttpa.sd %f29,%f30,%f31 + 1d4: 00 00 00 a0 shl %r0,%r0,%r0 + 1d8: 8b b7 1a 4b d.m12ttpa.dd %f22,%f24,%f26 + 1dc: 00 00 00 a0 shl %r0,%r0,%r0 + 1e0: 0c a6 b6 4a d.iat1p2.ss %f20,%f21,%f22 + 1e4: 00 00 00 a0 shl %r0,%r0,%r0 + 1e8: 8c 06 22 48 d.iat1p2.sd %f0,%f1,%f2 + 1ec: 00 00 00 a0 shl %r0,%r0,%r0 + 1f0: 8c c7 5c 4b d.iat1p2.dd %f24,%f26,%f28 + 1f4: 00 00 00 a0 shl %r0,%r0,%r0 + 1f8: 0d ae d7 4a d.m12tpm.ss %f21,%f22,%f23 + 1fc: 00 00 00 a0 shl %r0,%r0,%r0 + 200: 8d 1e 85 48 d.m12tpm.sd %f3,%f4,%f5 + 204: 00 00 00 a0 shl %r0,%r0,%r0 + 208: 8d f7 02 48 d.m12tpm.dd %f30,%f0,%f2 + 20c: 00 00 00 a0 shl %r0,%r0,%r0 + 210: 0e b6 f8 4a d.ia1p2.ss %f22,%f23,%f24 + 214: 00 00 00 a0 shl %r0,%r0,%r0 + 218: 8e 36 e8 48 d.ia1p2.sd %f6,%f7,%f8 + 21c: 00 00 00 a0 shl %r0,%r0,%r0 + 220: 8e 27 c8 48 d.ia1p2.dd %f4,%f6,%f8 + 224: 00 00 00 a0 shl %r0,%r0,%r0 + 228: 0f be 19 4b d.m12tpa.ss %f23,%f24,%f25 + 22c: 00 00 00 a0 shl %r0,%r0,%r0 + 230: 8f 4e 4b 49 d.m12tpa.sd %f9,%f10,%f11 + 234: 00 00 00 a0 shl %r0,%r0,%r0 + 238: 8f 37 0a 49 d.m12tpa.dd %f6,%f8,%f10 + 23c: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/pfam.s b/gas/testsuite/gas/i860/pfam.s new file mode 100644 index 00000000000..4afc28d1abb --- /dev/null +++ b/gas/testsuite/gas/i860/pfam.s @@ -0,0 +1,182 @@ +# pfam.p family (p={ss,sd,dd}) + + .text + + # pfam without dual bit. + r2p1.ss %f0,%f1,%f2 + r2p1.sd %f3,%f4,%f5 + r2p1.dd %f0,%f2,%f4 + + r2pt.ss %f1,%f2,%f3 + r2pt.sd %f4,%f5,%f6 + r2pt.dd %f2,%f4,%f6 + + r2ap1.ss %f2,%f3,%f4 + r2ap1.sd %f6,%f7,%f8 + r2ap1.dd %f4,%f6,%f8 + + r2apt.ss %f3,%f4,%f5 + r2apt.sd %f7,%f8,%f9 + r2apt.dd %f6,%f8,%f10 + + i2p1.ss %f4,%f5,%f6 + i2p1.sd %f8,%f9,%f10 + i2p1.dd %f12,%f14,%f16 + + i2pt.ss %f7,%f8,%f9 + i2pt.sd %f11,%f12,%f13 + i2pt.dd %f14,%f16,%f18 + + i2ap1.ss %f10,%f11,%f12 + i2ap1.sd %f14,%f15,%f16 + i2ap1.dd %f16,%f18,%f20 + + i2apt.ss %f13,%f14,%f15 + i2apt.sd %f17,%f18,%f19 + i2apt.dd %f18,%f20,%f22 + + rat1p2.ss %f14,%f15,%f16 + rat1p2.sd %f20,%f21,%f22 + rat1p2.dd %f20,%f22,%f24 + + m12apm.ss %f15,%f16,%f17 + m12apm.sd %f23,%f24,%f25 + m12apm.dd %f22,%f24,%f26 + + ra1p2.ss %f18,%f19,%f20 + ra1p2.sd %f26,%f27,%f28 + ra1p2.dd %f20,%f22,%f24 + + m12ttpa.ss %f19,%f20,%f21 + m12ttpa.sd %f29,%f30,%f31 + m12ttpa.dd %f22,%f24,%f26 + + iat1p2.ss %f20,%f21,%f22 + iat1p2.sd %f0,%f1,%f2 + iat1p2.dd %f24,%f26,%f28 + + m12tpm.ss %f21,%f22,%f23 + m12tpm.sd %f3,%f4,%f5 + m12tpm.dd %f30,%f0,%f2 + + ia1p2.ss %f22,%f23,%f24 + ia1p2.sd %f6,%f7,%f8 + ia1p2.dd %f4,%f6,%f8 + + m12tpa.ss %f23,%f24,%f25 + m12tpa.sd %f9,%f10,%f11 + m12tpa.dd %f6,%f8,%f10 + + # pfam with dual bit. + d.r2p1.ss %f0,%f1,%f2 + nop + d.r2p1.sd %f3,%f4,%f5 + nop + d.r2p1.dd %f0,%f2,%f4 + nop + + d.r2pt.ss %f1,%f2,%f3 + nop + d.r2pt.sd %f4,%f5,%f6 + nop + d.r2pt.dd %f2,%f4,%f6 + nop + + d.r2ap1.ss %f2,%f3,%f4 + nop + d.r2ap1.sd %f6,%f7,%f8 + nop + d.r2ap1.dd %f4,%f6,%f8 + nop + + d.r2apt.ss %f3,%f4,%f5 + nop + d.r2apt.sd %f7,%f8,%f9 + nop + d.r2apt.dd %f6,%f8,%f10 + nop + + d.i2p1.ss %f4,%f5,%f6 + nop + d.i2p1.sd %f8,%f9,%f10 + nop + d.i2p1.dd %f12,%f14,%f16 + nop + + d.i2pt.ss %f7,%f8,%f9 + nop + d.i2pt.sd %f11,%f12,%f13 + nop + d.i2pt.dd %f14,%f16,%f18 + nop + + d.i2ap1.ss %f10,%f11,%f12 + nop + d.i2ap1.sd %f14,%f15,%f16 + nop + d.i2ap1.dd %f16,%f18,%f20 + nop + + d.i2apt.ss %f13,%f14,%f15 + nop + d.i2apt.sd %f17,%f18,%f19 + nop + d.i2apt.dd %f18,%f20,%f22 + nop + + d.rat1p2.ss %f14,%f15,%f16 + nop + d.rat1p2.sd %f20,%f21,%f22 + nop + d.rat1p2.dd %f20,%f22,%f24 + nop + + d.m12apm.ss %f15,%f16,%f17 + nop + d.m12apm.sd %f23,%f24,%f25 + nop + d.m12apm.dd %f22,%f24,%f26 + nop + + d.ra1p2.ss %f18,%f19,%f20 + nop + d.ra1p2.sd %f26,%f27,%f28 + nop + d.ra1p2.dd %f20,%f22,%f24 + nop + + d.m12ttpa.ss %f19,%f20,%f21 + nop + d.m12ttpa.sd %f29,%f30,%f31 + nop + d.m12ttpa.dd %f22,%f24,%f26 + nop + + d.iat1p2.ss %f20,%f21,%f22 + nop + d.iat1p2.sd %f0,%f1,%f2 + nop + d.iat1p2.dd %f24,%f26,%f28 + nop + + d.m12tpm.ss %f21,%f22,%f23 + nop + d.m12tpm.sd %f3,%f4,%f5 + nop + d.m12tpm.dd %f30,%f0,%f2 + nop + + d.ia1p2.ss %f22,%f23,%f24 + nop + d.ia1p2.sd %f6,%f7,%f8 + nop + d.ia1p2.dd %f4,%f6,%f8 + nop + + d.m12tpa.ss %f23,%f24,%f25 + nop + d.m12tpa.sd %f9,%f10,%f11 + nop + d.m12tpa.dd %f6,%f8,%f10 + nop + diff --git a/gas/testsuite/gas/i860/pfmam.d b/gas/testsuite/gas/i860/pfmam.d new file mode 100644 index 00000000000..63f48a4c4c8 --- /dev/null +++ b/gas/testsuite/gas/i860/pfmam.d @@ -0,0 +1,153 @@ +#as: +#objdump: -dr +#name: i860 pfmam + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 22 48 mr2p1.ss %f0,%f1,%f2 + 4: 80 18 85 48 mr2p1.sd %f3,%f4,%f5 + 8: 80 01 44 48 mr2p1.dd %f0,%f2,%f4 + c: 01 08 43 48 mr2pt.ss %f1,%f2,%f3 + 10: 81 20 a6 48 mr2pt.sd %f4,%f5,%f6 + 14: 81 11 86 48 mr2pt.dd %f2,%f4,%f6 + 18: 02 10 64 48 mr2mp1.ss %f2,%f3,%f4 + 1c: 82 30 e8 48 mr2mp1.sd %f6,%f7,%f8 + 20: 82 21 c8 48 mr2mp1.dd %f4,%f6,%f8 + 24: 03 18 85 48 mr2mpt.ss %f3,%f4,%f5 + 28: 83 38 09 49 mr2mpt.sd %f7,%f8,%f9 + 2c: 83 31 0a 49 mr2mpt.dd %f6,%f8,%f10 + 30: 04 20 a6 48 mi2p1.ss %f4,%f5,%f6 + 34: 84 40 2a 49 mi2p1.sd %f8,%f9,%f10 + 38: 84 61 d0 49 mi2p1.dd %f12,%f14,%f16 + 3c: 05 38 09 49 mi2pt.ss %f7,%f8,%f9 + 40: 85 58 8d 49 mi2pt.sd %f11,%f12,%f13 + 44: 85 71 12 4a mi2pt.dd %f14,%f16,%f18 + 48: 06 50 6c 49 mi2mp1.ss %f10,%f11,%f12 + 4c: 86 70 f0 49 mi2mp1.sd %f14,%f15,%f16 + 50: 86 81 54 4a mi2mp1.dd %f16,%f18,%f20 + 54: 07 68 cf 49 mi2mpt.ss %f13,%f14,%f15 + 58: 87 88 53 4a mi2mpt.sd %f17,%f18,%f19 + 5c: 87 91 96 4a mi2mpt.dd %f18,%f20,%f22 + 60: 08 70 f0 49 mrmt1p2.ss %f14,%f15,%f16 + 64: 88 a0 b6 4a mrmt1p2.sd %f20,%f21,%f22 + 68: 88 a1 d8 4a mrmt1p2.dd %f20,%f22,%f24 + 6c: 09 78 11 4a mm12mpm.ss %f15,%f16,%f17 + 70: 89 b8 19 4b mm12mpm.sd %f23,%f24,%f25 + 74: 89 b1 1a 4b mm12mpm.dd %f22,%f24,%f26 + 78: 0a 90 74 4a mrm1p2.ss %f18,%f19,%f20 + 7c: 8a d0 7c 4b mrm1p2.sd %f26,%f27,%f28 + 80: 8a a1 d8 4a mrm1p2.dd %f20,%f22,%f24 + 84: 0b 98 95 4a mm12ttpm.ss %f19,%f20,%f21 + 88: 8b e8 df 4b mm12ttpm.sd %f29,%f30,%f31 + 8c: 8b b1 1a 4b mm12ttpm.dd %f22,%f24,%f26 + 90: 0c a0 b6 4a mimt1p2.ss %f20,%f21,%f22 + 94: 8c 00 22 48 mimt1p2.sd %f0,%f1,%f2 + 98: 8c c1 5c 4b mimt1p2.dd %f24,%f26,%f28 + 9c: 0d a8 d7 4a mm12tpm.ss %f21,%f22,%f23 + a0: 8d 18 85 48 mm12tpm.sd %f3,%f4,%f5 + a4: 8d f1 02 48 mm12tpm.dd %f30,%f0,%f2 + a8: 0e b0 f8 4a mim1p2.ss %f22,%f23,%f24 + ac: 8e 30 e8 48 mim1p2.sd %f6,%f7,%f8 + b0: 8e 21 c8 48 mim1p2.dd %f4,%f6,%f8 + b4: 0f bc 19 4b m12tpa.ss %f23,%f24,%f25 + b8: 8f 4c 4b 49 m12tpa.sd %f9,%f10,%f11 + bc: 8f 35 0a 49 m12tpa.dd %f6,%f8,%f10 + c0: 00 02 22 48 d.mr2p1.ss %f0,%f1,%f2 + c4: 00 00 00 a0 shl %r0,%r0,%r0 + c8: 80 1a 85 48 d.mr2p1.sd %f3,%f4,%f5 + cc: 00 00 00 a0 shl %r0,%r0,%r0 + d0: 80 03 44 48 d.mr2p1.dd %f0,%f2,%f4 + d4: 00 00 00 a0 shl %r0,%r0,%r0 + d8: 01 0a 43 48 d.mr2pt.ss %f1,%f2,%f3 + dc: 00 00 00 a0 shl %r0,%r0,%r0 + e0: 81 22 a6 48 d.mr2pt.sd %f4,%f5,%f6 + e4: 00 00 00 a0 shl %r0,%r0,%r0 + e8: 81 13 86 48 d.mr2pt.dd %f2,%f4,%f6 + ec: 00 00 00 a0 shl %r0,%r0,%r0 + f0: 02 12 64 48 d.mr2mp1.ss %f2,%f3,%f4 + f4: 00 00 00 a0 shl %r0,%r0,%r0 + f8: 82 32 e8 48 d.mr2mp1.sd %f6,%f7,%f8 + fc: 00 00 00 a0 shl %r0,%r0,%r0 + 100: 82 23 c8 48 d.mr2mp1.dd %f4,%f6,%f8 + 104: 00 00 00 a0 shl %r0,%r0,%r0 + 108: 03 1a 85 48 d.mr2mpt.ss %f3,%f4,%f5 + 10c: 00 00 00 a0 shl %r0,%r0,%r0 + 110: 83 3a 09 49 d.mr2mpt.sd %f7,%f8,%f9 + 114: 00 00 00 a0 shl %r0,%r0,%r0 + 118: 83 33 0a 49 d.mr2mpt.dd %f6,%f8,%f10 + 11c: 00 00 00 a0 shl %r0,%r0,%r0 + 120: 04 22 a6 48 d.mi2p1.ss %f4,%f5,%f6 + 124: 00 00 00 a0 shl %r0,%r0,%r0 + 128: 84 42 2a 49 d.mi2p1.sd %f8,%f9,%f10 + 12c: 00 00 00 a0 shl %r0,%r0,%r0 + 130: 84 63 d0 49 d.mi2p1.dd %f12,%f14,%f16 + 134: 00 00 00 a0 shl %r0,%r0,%r0 + 138: 05 3a 09 49 d.mi2pt.ss %f7,%f8,%f9 + 13c: 00 00 00 a0 shl %r0,%r0,%r0 + 140: 85 5a 8d 49 d.mi2pt.sd %f11,%f12,%f13 + 144: 00 00 00 a0 shl %r0,%r0,%r0 + 148: 85 73 12 4a d.mi2pt.dd %f14,%f16,%f18 + 14c: 00 00 00 a0 shl %r0,%r0,%r0 + 150: 06 52 6c 49 d.mi2mp1.ss %f10,%f11,%f12 + 154: 00 00 00 a0 shl %r0,%r0,%r0 + 158: 86 72 f0 49 d.mi2mp1.sd %f14,%f15,%f16 + 15c: 00 00 00 a0 shl %r0,%r0,%r0 + 160: 86 83 54 4a d.mi2mp1.dd %f16,%f18,%f20 + 164: 00 00 00 a0 shl %r0,%r0,%r0 + 168: 07 6a cf 49 d.mi2mpt.ss %f13,%f14,%f15 + 16c: 00 00 00 a0 shl %r0,%r0,%r0 + 170: 87 8a 53 4a d.mi2mpt.sd %f17,%f18,%f19 + 174: 00 00 00 a0 shl %r0,%r0,%r0 + 178: 87 93 96 4a d.mi2mpt.dd %f18,%f20,%f22 + 17c: 00 00 00 a0 shl %r0,%r0,%r0 + 180: 08 72 f0 49 d.mrmt1p2.ss %f14,%f15,%f16 + 184: 00 00 00 a0 shl %r0,%r0,%r0 + 188: 88 a2 b6 4a d.mrmt1p2.sd %f20,%f21,%f22 + 18c: 00 00 00 a0 shl %r0,%r0,%r0 + 190: 88 a3 d8 4a d.mrmt1p2.dd %f20,%f22,%f24 + 194: 00 00 00 a0 shl %r0,%r0,%r0 + 198: 09 7a 11 4a d.mm12mpm.ss %f15,%f16,%f17 + 19c: 00 00 00 a0 shl %r0,%r0,%r0 + 1a0: 89 ba 19 4b d.mm12mpm.sd %f23,%f24,%f25 + 1a4: 00 00 00 a0 shl %r0,%r0,%r0 + 1a8: 89 b3 1a 4b d.mm12mpm.dd %f22,%f24,%f26 + 1ac: 00 00 00 a0 shl %r0,%r0,%r0 + 1b0: 0a 92 74 4a d.mrm1p2.ss %f18,%f19,%f20 + 1b4: 00 00 00 a0 shl %r0,%r0,%r0 + 1b8: 8a d2 7c 4b d.mrm1p2.sd %f26,%f27,%f28 + 1bc: 00 00 00 a0 shl %r0,%r0,%r0 + 1c0: 8a a3 d8 4a d.mrm1p2.dd %f20,%f22,%f24 + 1c4: 00 00 00 a0 shl %r0,%r0,%r0 + 1c8: 0b 9a 95 4a d.mm12ttpm.ss %f19,%f20,%f21 + 1cc: 00 00 00 a0 shl %r0,%r0,%r0 + 1d0: 8b ea df 4b d.mm12ttpm.sd %f29,%f30,%f31 + 1d4: 00 00 00 a0 shl %r0,%r0,%r0 + 1d8: 8b b3 1a 4b d.mm12ttpm.dd %f22,%f24,%f26 + 1dc: 00 00 00 a0 shl %r0,%r0,%r0 + 1e0: 0c a2 b6 4a d.mimt1p2.ss %f20,%f21,%f22 + 1e4: 00 00 00 a0 shl %r0,%r0,%r0 + 1e8: 8c 02 22 48 d.mimt1p2.sd %f0,%f1,%f2 + 1ec: 00 00 00 a0 shl %r0,%r0,%r0 + 1f0: 8c c3 5c 4b d.mimt1p2.dd %f24,%f26,%f28 + 1f4: 00 00 00 a0 shl %r0,%r0,%r0 + 1f8: 0d aa d7 4a d.mm12tpm.ss %f21,%f22,%f23 + 1fc: 00 00 00 a0 shl %r0,%r0,%r0 + 200: 8d 1a 85 48 d.mm12tpm.sd %f3,%f4,%f5 + 204: 00 00 00 a0 shl %r0,%r0,%r0 + 208: 8d f3 02 48 d.mm12tpm.dd %f30,%f0,%f2 + 20c: 00 00 00 a0 shl %r0,%r0,%r0 + 210: 0e b2 f8 4a d.mim1p2.ss %f22,%f23,%f24 + 214: 00 00 00 a0 shl %r0,%r0,%r0 + 218: 8e 32 e8 48 d.mim1p2.sd %f6,%f7,%f8 + 21c: 00 00 00 a0 shl %r0,%r0,%r0 + 220: 8e 23 c8 48 d.mim1p2.dd %f4,%f6,%f8 + 224: 00 00 00 a0 shl %r0,%r0,%r0 + 228: 0f be 19 4b d.m12tpa.ss %f23,%f24,%f25 + 22c: 00 00 00 a0 shl %r0,%r0,%r0 + 230: 8f 4e 4b 49 d.m12tpa.sd %f9,%f10,%f11 + 234: 00 00 00 a0 shl %r0,%r0,%r0 + 238: 8f 37 0a 49 d.m12tpa.dd %f6,%f8,%f10 + 23c: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/pfmam.s b/gas/testsuite/gas/i860/pfmam.s new file mode 100644 index 00000000000..ac6a1afaf2b --- /dev/null +++ b/gas/testsuite/gas/i860/pfmam.s @@ -0,0 +1,182 @@ +# pfmam.p family (p={ss,sd,dd}) + + .text + + # pfmam without dual bit. + mr2p1.ss %f0,%f1,%f2 + mr2p1.sd %f3,%f4,%f5 + mr2p1.dd %f0,%f2,%f4 + + mr2pt.ss %f1,%f2,%f3 + mr2pt.sd %f4,%f5,%f6 + mr2pt.dd %f2,%f4,%f6 + + mr2mp1.ss %f2,%f3,%f4 + mr2mp1.sd %f6,%f7,%f8 + mr2mp1.dd %f4,%f6,%f8 + + mr2mpt.ss %f3,%f4,%f5 + mr2mpt.sd %f7,%f8,%f9 + mr2mpt.dd %f6,%f8,%f10 + + mi2p1.ss %f4,%f5,%f6 + mi2p1.sd %f8,%f9,%f10 + mi2p1.dd %f12,%f14,%f16 + + mi2pt.ss %f7,%f8,%f9 + mi2pt.sd %f11,%f12,%f13 + mi2pt.dd %f14,%f16,%f18 + + mi2mp1.ss %f10,%f11,%f12 + mi2mp1.sd %f14,%f15,%f16 + mi2mp1.dd %f16,%f18,%f20 + + mi2mpt.ss %f13,%f14,%f15 + mi2mpt.sd %f17,%f18,%f19 + mi2mpt.dd %f18,%f20,%f22 + + mrmt1p2.ss %f14,%f15,%f16 + mrmt1p2.sd %f20,%f21,%f22 + mrmt1p2.dd %f20,%f22,%f24 + + mm12mpm.ss %f15,%f16,%f17 + mm12mpm.sd %f23,%f24,%f25 + mm12mpm.dd %f22,%f24,%f26 + + mrm1p2.ss %f18,%f19,%f20 + mrm1p2.sd %f26,%f27,%f28 + mrm1p2.dd %f20,%f22,%f24 + + mm12ttpm.ss %f19,%f20,%f21 + mm12ttpm.sd %f29,%f30,%f31 + mm12ttpm.dd %f22,%f24,%f26 + + mimt1p2.ss %f20,%f21,%f22 + mimt1p2.sd %f0,%f1,%f2 + mimt1p2.dd %f24,%f26,%f28 + + mm12tpm.ss %f21,%f22,%f23 + mm12tpm.sd %f3,%f4,%f5 + mm12tpm.dd %f30,%f0,%f2 + + mim1p2.ss %f22,%f23,%f24 + mim1p2.sd %f6,%f7,%f8 + mim1p2.dd %f4,%f6,%f8 + + m12tpa.ss %f23,%f24,%f25 + m12tpa.sd %f9,%f10,%f11 + m12tpa.dd %f6,%f8,%f10 + + # pfmam with dual bit. + d.mr2p1.ss %f0,%f1,%f2 + nop + d.mr2p1.sd %f3,%f4,%f5 + nop + d.mr2p1.dd %f0,%f2,%f4 + nop + + d.mr2pt.ss %f1,%f2,%f3 + nop + d.mr2pt.sd %f4,%f5,%f6 + nop + d.mr2pt.dd %f2,%f4,%f6 + nop + + d.mr2mp1.ss %f2,%f3,%f4 + nop + d.mr2mp1.sd %f6,%f7,%f8 + nop + d.mr2mp1.dd %f4,%f6,%f8 + nop + + d.mr2mpt.ss %f3,%f4,%f5 + nop + d.mr2mpt.sd %f7,%f8,%f9 + nop + d.mr2mpt.dd %f6,%f8,%f10 + nop + + d.mi2p1.ss %f4,%f5,%f6 + nop + d.mi2p1.sd %f8,%f9,%f10 + nop + d.mi2p1.dd %f12,%f14,%f16 + nop + + d.mi2pt.ss %f7,%f8,%f9 + nop + d.mi2pt.sd %f11,%f12,%f13 + nop + d.mi2pt.dd %f14,%f16,%f18 + nop + + d.mi2mp1.ss %f10,%f11,%f12 + nop + d.mi2mp1.sd %f14,%f15,%f16 + nop + d.mi2mp1.dd %f16,%f18,%f20 + nop + + d.mi2mpt.ss %f13,%f14,%f15 + nop + d.mi2mpt.sd %f17,%f18,%f19 + nop + d.mi2mpt.dd %f18,%f20,%f22 + nop + + d.mrmt1p2.ss %f14,%f15,%f16 + nop + d.mrmt1p2.sd %f20,%f21,%f22 + nop + d.mrmt1p2.dd %f20,%f22,%f24 + nop + + d.mm12mpm.ss %f15,%f16,%f17 + nop + d.mm12mpm.sd %f23,%f24,%f25 + nop + d.mm12mpm.dd %f22,%f24,%f26 + nop + + d.mrm1p2.ss %f18,%f19,%f20 + nop + d.mrm1p2.sd %f26,%f27,%f28 + nop + d.mrm1p2.dd %f20,%f22,%f24 + nop + + d.mm12ttpm.ss %f19,%f20,%f21 + nop + d.mm12ttpm.sd %f29,%f30,%f31 + nop + d.mm12ttpm.dd %f22,%f24,%f26 + nop + + d.mimt1p2.ss %f20,%f21,%f22 + nop + d.mimt1p2.sd %f0,%f1,%f2 + nop + d.mimt1p2.dd %f24,%f26,%f28 + nop + + d.mm12tpm.ss %f21,%f22,%f23 + nop + d.mm12tpm.sd %f3,%f4,%f5 + nop + d.mm12tpm.dd %f30,%f0,%f2 + nop + + d.mim1p2.ss %f22,%f23,%f24 + nop + d.mim1p2.sd %f6,%f7,%f8 + nop + d.mim1p2.dd %f4,%f6,%f8 + nop + + d.m12tpa.ss %f23,%f24,%f25 + nop + d.m12tpa.sd %f9,%f10,%f11 + nop + d.m12tpa.dd %f6,%f8,%f10 + nop + diff --git a/gas/testsuite/gas/i860/pfmsm.d b/gas/testsuite/gas/i860/pfmsm.d new file mode 100644 index 00000000000..65d7e978969 --- /dev/null +++ b/gas/testsuite/gas/i860/pfmsm.d @@ -0,0 +1,153 @@ +#as: +#objdump: -dr +#name: i860 pfmsm + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 10 00 22 48 mr2s1.ss %f0,%f1,%f2 + 4: 90 18 85 48 mr2s1.sd %f3,%f4,%f5 + 8: 90 01 44 48 mr2s1.dd %f0,%f2,%f4 + c: 11 08 43 48 mr2st.ss %f1,%f2,%f3 + 10: 91 20 a6 48 mr2st.sd %f4,%f5,%f6 + 14: 91 11 86 48 mr2st.dd %f2,%f4,%f6 + 18: 12 10 64 48 mr2ms1.ss %f2,%f3,%f4 + 1c: 92 30 e8 48 mr2ms1.sd %f6,%f7,%f8 + 20: 92 21 c8 48 mr2ms1.dd %f4,%f6,%f8 + 24: 13 18 85 48 mr2mst.ss %f3,%f4,%f5 + 28: 93 38 09 49 mr2mst.sd %f7,%f8,%f9 + 2c: 93 31 0a 49 mr2mst.dd %f6,%f8,%f10 + 30: 14 20 a6 48 mi2s1.ss %f4,%f5,%f6 + 34: 94 40 2a 49 mi2s1.sd %f8,%f9,%f10 + 38: 94 61 d0 49 mi2s1.dd %f12,%f14,%f16 + 3c: 15 38 09 49 mi2st.ss %f7,%f8,%f9 + 40: 95 58 8d 49 mi2st.sd %f11,%f12,%f13 + 44: 95 71 12 4a mi2st.dd %f14,%f16,%f18 + 48: 16 50 6c 49 mi2ms1.ss %f10,%f11,%f12 + 4c: 96 70 f0 49 mi2ms1.sd %f14,%f15,%f16 + 50: 96 81 54 4a mi2ms1.dd %f16,%f18,%f20 + 54: 17 68 cf 49 mi2mst.ss %f13,%f14,%f15 + 58: 97 88 53 4a mi2mst.sd %f17,%f18,%f19 + 5c: 97 91 96 4a mi2mst.dd %f18,%f20,%f22 + 60: 18 70 f0 49 mrmt1s2.ss %f14,%f15,%f16 + 64: 98 a0 b6 4a mrmt1s2.sd %f20,%f21,%f22 + 68: 98 a1 d8 4a mrmt1s2.dd %f20,%f22,%f24 + 6c: 19 78 11 4a mm12msm.ss %f15,%f16,%f17 + 70: 99 b8 19 4b mm12msm.sd %f23,%f24,%f25 + 74: 99 b1 1a 4b mm12msm.dd %f22,%f24,%f26 + 78: 1a 90 74 4a mrm1s2.ss %f18,%f19,%f20 + 7c: 9a d0 7c 4b mrm1s2.sd %f26,%f27,%f28 + 80: 9a a1 d8 4a mrm1s2.dd %f20,%f22,%f24 + 84: 1b 98 95 4a mm12ttsm.ss %f19,%f20,%f21 + 88: 9b e8 df 4b mm12ttsm.sd %f29,%f30,%f31 + 8c: 9b b1 1a 4b mm12ttsm.dd %f22,%f24,%f26 + 90: 1c a0 b6 4a mimt1s2.ss %f20,%f21,%f22 + 94: 9c 00 22 48 mimt1s2.sd %f0,%f1,%f2 + 98: 9c c1 5c 4b mimt1s2.dd %f24,%f26,%f28 + 9c: 1d a8 d7 4a mm12tsm.ss %f21,%f22,%f23 + a0: 9d 18 85 48 mm12tsm.sd %f3,%f4,%f5 + a4: 9d f1 02 48 mm12tsm.dd %f30,%f0,%f2 + a8: 1e b0 f8 4a mim1s2.ss %f22,%f23,%f24 + ac: 9e 30 e8 48 mim1s2.sd %f6,%f7,%f8 + b0: 9e 21 c8 48 mim1s2.dd %f4,%f6,%f8 + b4: 1f bc 19 4b m12tsa.ss %f23,%f24,%f25 + b8: 9f 4c 4b 49 m12tsa.sd %f9,%f10,%f11 + bc: 9f 35 0a 49 m12tsa.dd %f6,%f8,%f10 + c0: 10 02 22 48 d.mr2s1.ss %f0,%f1,%f2 + c4: 00 00 00 a0 shl %r0,%r0,%r0 + c8: 90 1a 85 48 d.mr2s1.sd %f3,%f4,%f5 + cc: 00 00 00 a0 shl %r0,%r0,%r0 + d0: 90 03 44 48 d.mr2s1.dd %f0,%f2,%f4 + d4: 00 00 00 a0 shl %r0,%r0,%r0 + d8: 11 0a 43 48 d.mr2st.ss %f1,%f2,%f3 + dc: 00 00 00 a0 shl %r0,%r0,%r0 + e0: 91 22 a6 48 d.mr2st.sd %f4,%f5,%f6 + e4: 00 00 00 a0 shl %r0,%r0,%r0 + e8: 91 13 86 48 d.mr2st.dd %f2,%f4,%f6 + ec: 00 00 00 a0 shl %r0,%r0,%r0 + f0: 12 12 64 48 d.mr2ms1.ss %f2,%f3,%f4 + f4: 00 00 00 a0 shl %r0,%r0,%r0 + f8: 92 32 e8 48 d.mr2ms1.sd %f6,%f7,%f8 + fc: 00 00 00 a0 shl %r0,%r0,%r0 + 100: 92 23 c8 48 d.mr2ms1.dd %f4,%f6,%f8 + 104: 00 00 00 a0 shl %r0,%r0,%r0 + 108: 13 1a 85 48 d.mr2mst.ss %f3,%f4,%f5 + 10c: 00 00 00 a0 shl %r0,%r0,%r0 + 110: 93 3a 09 49 d.mr2mst.sd %f7,%f8,%f9 + 114: 00 00 00 a0 shl %r0,%r0,%r0 + 118: 93 33 0a 49 d.mr2mst.dd %f6,%f8,%f10 + 11c: 00 00 00 a0 shl %r0,%r0,%r0 + 120: 14 22 a6 48 d.mi2s1.ss %f4,%f5,%f6 + 124: 00 00 00 a0 shl %r0,%r0,%r0 + 128: 94 42 2a 49 d.mi2s1.sd %f8,%f9,%f10 + 12c: 00 00 00 a0 shl %r0,%r0,%r0 + 130: 94 63 d0 49 d.mi2s1.dd %f12,%f14,%f16 + 134: 00 00 00 a0 shl %r0,%r0,%r0 + 138: 15 3a 09 49 d.mi2st.ss %f7,%f8,%f9 + 13c: 00 00 00 a0 shl %r0,%r0,%r0 + 140: 95 5a 8d 49 d.mi2st.sd %f11,%f12,%f13 + 144: 00 00 00 a0 shl %r0,%r0,%r0 + 148: 95 73 12 4a d.mi2st.dd %f14,%f16,%f18 + 14c: 00 00 00 a0 shl %r0,%r0,%r0 + 150: 16 52 6c 49 d.mi2ms1.ss %f10,%f11,%f12 + 154: 00 00 00 a0 shl %r0,%r0,%r0 + 158: 96 72 f0 49 d.mi2ms1.sd %f14,%f15,%f16 + 15c: 00 00 00 a0 shl %r0,%r0,%r0 + 160: 96 83 54 4a d.mi2ms1.dd %f16,%f18,%f20 + 164: 00 00 00 a0 shl %r0,%r0,%r0 + 168: 17 6a cf 49 d.mi2mst.ss %f13,%f14,%f15 + 16c: 00 00 00 a0 shl %r0,%r0,%r0 + 170: 97 8a 53 4a d.mi2mst.sd %f17,%f18,%f19 + 174: 00 00 00 a0 shl %r0,%r0,%r0 + 178: 97 93 96 4a d.mi2mst.dd %f18,%f20,%f22 + 17c: 00 00 00 a0 shl %r0,%r0,%r0 + 180: 18 72 f0 49 d.mrmt1s2.ss %f14,%f15,%f16 + 184: 00 00 00 a0 shl %r0,%r0,%r0 + 188: 98 a2 b6 4a d.mrmt1s2.sd %f20,%f21,%f22 + 18c: 00 00 00 a0 shl %r0,%r0,%r0 + 190: 98 a3 d8 4a d.mrmt1s2.dd %f20,%f22,%f24 + 194: 00 00 00 a0 shl %r0,%r0,%r0 + 198: 19 7a 11 4a d.mm12msm.ss %f15,%f16,%f17 + 19c: 00 00 00 a0 shl %r0,%r0,%r0 + 1a0: 99 ba 19 4b d.mm12msm.sd %f23,%f24,%f25 + 1a4: 00 00 00 a0 shl %r0,%r0,%r0 + 1a8: 99 b3 1a 4b d.mm12msm.dd %f22,%f24,%f26 + 1ac: 00 00 00 a0 shl %r0,%r0,%r0 + 1b0: 1a 92 74 4a d.mrm1s2.ss %f18,%f19,%f20 + 1b4: 00 00 00 a0 shl %r0,%r0,%r0 + 1b8: 9a d2 7c 4b d.mrm1s2.sd %f26,%f27,%f28 + 1bc: 00 00 00 a0 shl %r0,%r0,%r0 + 1c0: 9a a3 d8 4a d.mrm1s2.dd %f20,%f22,%f24 + 1c4: 00 00 00 a0 shl %r0,%r0,%r0 + 1c8: 1b 9a 95 4a d.mm12ttsm.ss %f19,%f20,%f21 + 1cc: 00 00 00 a0 shl %r0,%r0,%r0 + 1d0: 9b ea df 4b d.mm12ttsm.sd %f29,%f30,%f31 + 1d4: 00 00 00 a0 shl %r0,%r0,%r0 + 1d8: 9b b3 1a 4b d.mm12ttsm.dd %f22,%f24,%f26 + 1dc: 00 00 00 a0 shl %r0,%r0,%r0 + 1e0: 1c a2 b6 4a d.mimt1s2.ss %f20,%f21,%f22 + 1e4: 00 00 00 a0 shl %r0,%r0,%r0 + 1e8: 9c 02 22 48 d.mimt1s2.sd %f0,%f1,%f2 + 1ec: 00 00 00 a0 shl %r0,%r0,%r0 + 1f0: 9c c3 5c 4b d.mimt1s2.dd %f24,%f26,%f28 + 1f4: 00 00 00 a0 shl %r0,%r0,%r0 + 1f8: 1d aa d7 4a d.mm12tsm.ss %f21,%f22,%f23 + 1fc: 00 00 00 a0 shl %r0,%r0,%r0 + 200: 9d 1a 85 48 d.mm12tsm.sd %f3,%f4,%f5 + 204: 00 00 00 a0 shl %r0,%r0,%r0 + 208: 9d f3 02 48 d.mm12tsm.dd %f30,%f0,%f2 + 20c: 00 00 00 a0 shl %r0,%r0,%r0 + 210: 1e b2 f8 4a d.mim1s2.ss %f22,%f23,%f24 + 214: 00 00 00 a0 shl %r0,%r0,%r0 + 218: 9e 32 e8 48 d.mim1s2.sd %f6,%f7,%f8 + 21c: 00 00 00 a0 shl %r0,%r0,%r0 + 220: 9e 23 c8 48 d.mim1s2.dd %f4,%f6,%f8 + 224: 00 00 00 a0 shl %r0,%r0,%r0 + 228: 1f be 19 4b d.m12tsa.ss %f23,%f24,%f25 + 22c: 00 00 00 a0 shl %r0,%r0,%r0 + 230: 9f 4e 4b 49 d.m12tsa.sd %f9,%f10,%f11 + 234: 00 00 00 a0 shl %r0,%r0,%r0 + 238: 9f 37 0a 49 d.m12tsa.dd %f6,%f8,%f10 + 23c: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/pfmsm.s b/gas/testsuite/gas/i860/pfmsm.s new file mode 100644 index 00000000000..26c91660db2 --- /dev/null +++ b/gas/testsuite/gas/i860/pfmsm.s @@ -0,0 +1,182 @@ +# pfmsm.p family (p={ss,sd,dd}) + + .text + + # pfmsm without dual bit + mr2s1.ss %f0,%f1,%f2 + mr2s1.sd %f3,%f4,%f5 + mr2s1.dd %f0,%f2,%f4 + + mr2st.ss %f1,%f2,%f3 + mr2st.sd %f4,%f5,%f6 + mr2st.dd %f2,%f4,%f6 + + mr2ms1.ss %f2,%f3,%f4 + mr2ms1.sd %f6,%f7,%f8 + mr2ms1.dd %f4,%f6,%f8 + + mr2mst.ss %f3,%f4,%f5 + mr2mst.sd %f7,%f8,%f9 + mr2mst.dd %f6,%f8,%f10 + + mi2s1.ss %f4,%f5,%f6 + mi2s1.sd %f8,%f9,%f10 + mi2s1.dd %f12,%f14,%f16 + + mi2st.ss %f7,%f8,%f9 + mi2st.sd %f11,%f12,%f13 + mi2st.dd %f14,%f16,%f18 + + mi2ms1.ss %f10,%f11,%f12 + mi2ms1.sd %f14,%f15,%f16 + mi2ms1.dd %f16,%f18,%f20 + + mi2mst.ss %f13,%f14,%f15 + mi2mst.sd %f17,%f18,%f19 + mi2mst.dd %f18,%f20,%f22 + + mrmt1s2.ss %f14,%f15,%f16 + mrmt1s2.sd %f20,%f21,%f22 + mrmt1s2.dd %f20,%f22,%f24 + + mm12msm.ss %f15,%f16,%f17 + mm12msm.sd %f23,%f24,%f25 + mm12msm.dd %f22,%f24,%f26 + + mrm1s2.ss %f18,%f19,%f20 + mrm1s2.sd %f26,%f27,%f28 + mrm1s2.dd %f20,%f22,%f24 + + mm12ttsm.ss %f19,%f20,%f21 + mm12ttsm.sd %f29,%f30,%f31 + mm12ttsm.dd %f22,%f24,%f26 + + mimt1s2.ss %f20,%f21,%f22 + mimt1s2.sd %f0,%f1,%f2 + mimt1s2.dd %f24,%f26,%f28 + + mm12tsm.ss %f21,%f22,%f23 + mm12tsm.sd %f3,%f4,%f5 + mm12tsm.dd %f30,%f0,%f2 + + mim1s2.ss %f22,%f23,%f24 + mim1s2.sd %f6,%f7,%f8 + mim1s2.dd %f4,%f6,%f8 + + m12tsa.ss %f23,%f24,%f25 + m12tsa.sd %f9,%f10,%f11 + m12tsa.dd %f6,%f8,%f10 + + # pfmsm with dual bit + d.mr2s1.ss %f0,%f1,%f2 + nop + d.mr2s1.sd %f3,%f4,%f5 + nop + d.mr2s1.dd %f0,%f2,%f4 + nop + + d.mr2st.ss %f1,%f2,%f3 + nop + d.mr2st.sd %f4,%f5,%f6 + nop + d.mr2st.dd %f2,%f4,%f6 + nop + + d.mr2ms1.ss %f2,%f3,%f4 + nop + d.mr2ms1.sd %f6,%f7,%f8 + nop + d.mr2ms1.dd %f4,%f6,%f8 + nop + + d.mr2mst.ss %f3,%f4,%f5 + nop + d.mr2mst.sd %f7,%f8,%f9 + nop + d.mr2mst.dd %f6,%f8,%f10 + nop + + d.mi2s1.ss %f4,%f5,%f6 + nop + d.mi2s1.sd %f8,%f9,%f10 + nop + d.mi2s1.dd %f12,%f14,%f16 + nop + + d.mi2st.ss %f7,%f8,%f9 + nop + d.mi2st.sd %f11,%f12,%f13 + nop + d.mi2st.dd %f14,%f16,%f18 + nop + + d.mi2ms1.ss %f10,%f11,%f12 + nop + d.mi2ms1.sd %f14,%f15,%f16 + nop + d.mi2ms1.dd %f16,%f18,%f20 + nop + + d.mi2mst.ss %f13,%f14,%f15 + nop + d.mi2mst.sd %f17,%f18,%f19 + nop + d.mi2mst.dd %f18,%f20,%f22 + nop + + d.mrmt1s2.ss %f14,%f15,%f16 + nop + d.mrmt1s2.sd %f20,%f21,%f22 + nop + d.mrmt1s2.dd %f20,%f22,%f24 + nop + + d.mm12msm.ss %f15,%f16,%f17 + nop + d.mm12msm.sd %f23,%f24,%f25 + nop + d.mm12msm.dd %f22,%f24,%f26 + nop + + d.mrm1s2.ss %f18,%f19,%f20 + nop + d.mrm1s2.sd %f26,%f27,%f28 + nop + d.mrm1s2.dd %f20,%f22,%f24 + nop + + d.mm12ttsm.ss %f19,%f20,%f21 + nop + d.mm12ttsm.sd %f29,%f30,%f31 + nop + d.mm12ttsm.dd %f22,%f24,%f26 + nop + + d.mimt1s2.ss %f20,%f21,%f22 + nop + d.mimt1s2.sd %f0,%f1,%f2 + nop + d.mimt1s2.dd %f24,%f26,%f28 + nop + + d.mm12tsm.ss %f21,%f22,%f23 + nop + d.mm12tsm.sd %f3,%f4,%f5 + nop + d.mm12tsm.dd %f30,%f0,%f2 + nop + + d.mim1s2.ss %f22,%f23,%f24 + nop + d.mim1s2.sd %f6,%f7,%f8 + nop + d.mim1s2.dd %f4,%f6,%f8 + nop + + d.m12tsa.ss %f23,%f24,%f25 + nop + d.m12tsa.sd %f9,%f10,%f11 + nop + d.m12tsa.dd %f6,%f8,%f10 + nop + diff --git a/gas/testsuite/gas/i860/pfsm.d b/gas/testsuite/gas/i860/pfsm.d new file mode 100644 index 00000000000..a3655cbd2e6 --- /dev/null +++ b/gas/testsuite/gas/i860/pfsm.d @@ -0,0 +1,153 @@ +#as: +#objdump: -dr +#name: i860 pfsm + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 10 04 22 48 r2s1.ss %f0,%f1,%f2 + 4: 90 1c 85 48 r2s1.sd %f3,%f4,%f5 + 8: 90 05 44 48 r2s1.dd %f0,%f2,%f4 + c: 11 0c 43 48 r2st.ss %f1,%f2,%f3 + 10: 91 24 a6 48 r2st.sd %f4,%f5,%f6 + 14: 91 15 86 48 r2st.dd %f2,%f4,%f6 + 18: 12 14 64 48 r2as1.ss %f2,%f3,%f4 + 1c: 92 34 e8 48 r2as1.sd %f6,%f7,%f8 + 20: 92 25 c8 48 r2as1.dd %f4,%f6,%f8 + 24: 13 1c 85 48 r2ast.ss %f3,%f4,%f5 + 28: 93 3c 09 49 r2ast.sd %f7,%f8,%f9 + 2c: 93 35 0a 49 r2ast.dd %f6,%f8,%f10 + 30: 14 24 a6 48 i2s1.ss %f4,%f5,%f6 + 34: 94 44 2a 49 i2s1.sd %f8,%f9,%f10 + 38: 94 65 d0 49 i2s1.dd %f12,%f14,%f16 + 3c: 15 3c 09 49 i2st.ss %f7,%f8,%f9 + 40: 95 5c 8d 49 i2st.sd %f11,%f12,%f13 + 44: 95 75 12 4a i2st.dd %f14,%f16,%f18 + 48: 16 54 6c 49 i2as1.ss %f10,%f11,%f12 + 4c: 96 74 f0 49 i2as1.sd %f14,%f15,%f16 + 50: 96 85 54 4a i2as1.dd %f16,%f18,%f20 + 54: 17 6c cf 49 i2ast.ss %f13,%f14,%f15 + 58: 97 8c 53 4a i2ast.sd %f17,%f18,%f19 + 5c: 97 95 96 4a i2ast.dd %f18,%f20,%f22 + 60: 18 74 f0 49 rat1s2.ss %f14,%f15,%f16 + 64: 98 a4 b6 4a rat1s2.sd %f20,%f21,%f22 + 68: 98 a5 d8 4a rat1s2.dd %f20,%f22,%f24 + 6c: 19 7c 11 4a m12asm.ss %f15,%f16,%f17 + 70: 99 bc 19 4b m12asm.sd %f23,%f24,%f25 + 74: 99 b5 1a 4b m12asm.dd %f22,%f24,%f26 + 78: 1a 94 74 4a ra1s2.ss %f18,%f19,%f20 + 7c: 9a d4 7c 4b ra1s2.sd %f26,%f27,%f28 + 80: 9a a5 d8 4a ra1s2.dd %f20,%f22,%f24 + 84: 1b 9c 95 4a m12ttsa.ss %f19,%f20,%f21 + 88: 9b ec df 4b m12ttsa.sd %f29,%f30,%f31 + 8c: 9b b5 1a 4b m12ttsa.dd %f22,%f24,%f26 + 90: 1c a4 b6 4a iat1s2.ss %f20,%f21,%f22 + 94: 9c 04 22 48 iat1s2.sd %f0,%f1,%f2 + 98: 9c c5 5c 4b iat1s2.dd %f24,%f26,%f28 + 9c: 1d ac d7 4a m12tsm.ss %f21,%f22,%f23 + a0: 9d 1c 85 48 m12tsm.sd %f3,%f4,%f5 + a4: 9d f5 02 48 m12tsm.dd %f30,%f0,%f2 + a8: 1e b4 f8 4a ia1s2.ss %f22,%f23,%f24 + ac: 9e 34 e8 48 ia1s2.sd %f6,%f7,%f8 + b0: 9e 25 c8 48 ia1s2.dd %f4,%f6,%f8 + b4: 1f bc 19 4b m12tsa.ss %f23,%f24,%f25 + b8: 9f 4c 4b 49 m12tsa.sd %f9,%f10,%f11 + bc: 9f 35 0a 49 m12tsa.dd %f6,%f8,%f10 + c0: 10 06 22 48 d.r2s1.ss %f0,%f1,%f2 + c4: 00 00 00 a0 shl %r0,%r0,%r0 + c8: 90 1e 85 48 d.r2s1.sd %f3,%f4,%f5 + cc: 00 00 00 a0 shl %r0,%r0,%r0 + d0: 90 07 44 48 d.r2s1.dd %f0,%f2,%f4 + d4: 00 00 00 a0 shl %r0,%r0,%r0 + d8: 11 0e 43 48 d.r2st.ss %f1,%f2,%f3 + dc: 00 00 00 a0 shl %r0,%r0,%r0 + e0: 91 26 a6 48 d.r2st.sd %f4,%f5,%f6 + e4: 00 00 00 a0 shl %r0,%r0,%r0 + e8: 91 17 86 48 d.r2st.dd %f2,%f4,%f6 + ec: 00 00 00 a0 shl %r0,%r0,%r0 + f0: 12 16 64 48 d.r2as1.ss %f2,%f3,%f4 + f4: 00 00 00 a0 shl %r0,%r0,%r0 + f8: 92 36 e8 48 d.r2as1.sd %f6,%f7,%f8 + fc: 00 00 00 a0 shl %r0,%r0,%r0 + 100: 92 27 c8 48 d.r2as1.dd %f4,%f6,%f8 + 104: 00 00 00 a0 shl %r0,%r0,%r0 + 108: 13 1e 85 48 d.r2ast.ss %f3,%f4,%f5 + 10c: 00 00 00 a0 shl %r0,%r0,%r0 + 110: 93 3e 09 49 d.r2ast.sd %f7,%f8,%f9 + 114: 00 00 00 a0 shl %r0,%r0,%r0 + 118: 93 37 0a 49 d.r2ast.dd %f6,%f8,%f10 + 11c: 00 00 00 a0 shl %r0,%r0,%r0 + 120: 14 26 a6 48 d.i2s1.ss %f4,%f5,%f6 + 124: 00 00 00 a0 shl %r0,%r0,%r0 + 128: 94 46 2a 49 d.i2s1.sd %f8,%f9,%f10 + 12c: 00 00 00 a0 shl %r0,%r0,%r0 + 130: 94 67 d0 49 d.i2s1.dd %f12,%f14,%f16 + 134: 00 00 00 a0 shl %r0,%r0,%r0 + 138: 15 3e 09 49 d.i2st.ss %f7,%f8,%f9 + 13c: 00 00 00 a0 shl %r0,%r0,%r0 + 140: 95 5e 8d 49 d.i2st.sd %f11,%f12,%f13 + 144: 00 00 00 a0 shl %r0,%r0,%r0 + 148: 95 77 12 4a d.i2st.dd %f14,%f16,%f18 + 14c: 00 00 00 a0 shl %r0,%r0,%r0 + 150: 16 56 6c 49 d.i2as1.ss %f10,%f11,%f12 + 154: 00 00 00 a0 shl %r0,%r0,%r0 + 158: 96 76 f0 49 d.i2as1.sd %f14,%f15,%f16 + 15c: 00 00 00 a0 shl %r0,%r0,%r0 + 160: 96 87 54 4a d.i2as1.dd %f16,%f18,%f20 + 164: 00 00 00 a0 shl %r0,%r0,%r0 + 168: 17 6e cf 49 d.i2ast.ss %f13,%f14,%f15 + 16c: 00 00 00 a0 shl %r0,%r0,%r0 + 170: 97 8e 53 4a d.i2ast.sd %f17,%f18,%f19 + 174: 00 00 00 a0 shl %r0,%r0,%r0 + 178: 97 97 96 4a d.i2ast.dd %f18,%f20,%f22 + 17c: 00 00 00 a0 shl %r0,%r0,%r0 + 180: 18 76 f0 49 d.rat1s2.ss %f14,%f15,%f16 + 184: 00 00 00 a0 shl %r0,%r0,%r0 + 188: 98 a6 b6 4a d.rat1s2.sd %f20,%f21,%f22 + 18c: 00 00 00 a0 shl %r0,%r0,%r0 + 190: 98 a7 d8 4a d.rat1s2.dd %f20,%f22,%f24 + 194: 00 00 00 a0 shl %r0,%r0,%r0 + 198: 19 7e 11 4a d.m12asm.ss %f15,%f16,%f17 + 19c: 00 00 00 a0 shl %r0,%r0,%r0 + 1a0: 99 be 19 4b d.m12asm.sd %f23,%f24,%f25 + 1a4: 00 00 00 a0 shl %r0,%r0,%r0 + 1a8: 99 b7 1a 4b d.m12asm.dd %f22,%f24,%f26 + 1ac: 00 00 00 a0 shl %r0,%r0,%r0 + 1b0: 1a 96 74 4a d.ra1s2.ss %f18,%f19,%f20 + 1b4: 00 00 00 a0 shl %r0,%r0,%r0 + 1b8: 9a d6 7c 4b d.ra1s2.sd %f26,%f27,%f28 + 1bc: 00 00 00 a0 shl %r0,%r0,%r0 + 1c0: 9a a7 d8 4a d.ra1s2.dd %f20,%f22,%f24 + 1c4: 00 00 00 a0 shl %r0,%r0,%r0 + 1c8: 1b 9e 95 4a d.m12ttsa.ss %f19,%f20,%f21 + 1cc: 00 00 00 a0 shl %r0,%r0,%r0 + 1d0: 9b ee df 4b d.m12ttsa.sd %f29,%f30,%f31 + 1d4: 00 00 00 a0 shl %r0,%r0,%r0 + 1d8: 9b b7 1a 4b d.m12ttsa.dd %f22,%f24,%f26 + 1dc: 00 00 00 a0 shl %r0,%r0,%r0 + 1e0: 1c a6 b6 4a d.iat1s2.ss %f20,%f21,%f22 + 1e4: 00 00 00 a0 shl %r0,%r0,%r0 + 1e8: 9c 06 22 48 d.iat1s2.sd %f0,%f1,%f2 + 1ec: 00 00 00 a0 shl %r0,%r0,%r0 + 1f0: 9c c7 5c 4b d.iat1s2.dd %f24,%f26,%f28 + 1f4: 00 00 00 a0 shl %r0,%r0,%r0 + 1f8: 1d ae d7 4a d.m12tsm.ss %f21,%f22,%f23 + 1fc: 00 00 00 a0 shl %r0,%r0,%r0 + 200: 9d 1e 85 48 d.m12tsm.sd %f3,%f4,%f5 + 204: 00 00 00 a0 shl %r0,%r0,%r0 + 208: 9d f7 02 48 d.m12tsm.dd %f30,%f0,%f2 + 20c: 00 00 00 a0 shl %r0,%r0,%r0 + 210: 1e b6 f8 4a d.ia1s2.ss %f22,%f23,%f24 + 214: 00 00 00 a0 shl %r0,%r0,%r0 + 218: 9e 36 e8 48 d.ia1s2.sd %f6,%f7,%f8 + 21c: 00 00 00 a0 shl %r0,%r0,%r0 + 220: 9e 27 c8 48 d.ia1s2.dd %f4,%f6,%f8 + 224: 00 00 00 a0 shl %r0,%r0,%r0 + 228: 1f be 19 4b d.m12tsa.ss %f23,%f24,%f25 + 22c: 00 00 00 a0 shl %r0,%r0,%r0 + 230: 9f 4e 4b 49 d.m12tsa.sd %f9,%f10,%f11 + 234: 00 00 00 a0 shl %r0,%r0,%r0 + 238: 9f 37 0a 49 d.m12tsa.dd %f6,%f8,%f10 + 23c: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/pfsm.s b/gas/testsuite/gas/i860/pfsm.s new file mode 100644 index 00000000000..16ecd979e49 --- /dev/null +++ b/gas/testsuite/gas/i860/pfsm.s @@ -0,0 +1,182 @@ +# pfsm.p family (p={ss,sd,dd}) + + .text + + # pfsm without dual bit + r2s1.ss %f0,%f1,%f2 + r2s1.sd %f3,%f4,%f5 + r2s1.dd %f0,%f2,%f4 + + r2st.ss %f1,%f2,%f3 + r2st.sd %f4,%f5,%f6 + r2st.dd %f2,%f4,%f6 + + r2as1.ss %f2,%f3,%f4 + r2as1.sd %f6,%f7,%f8 + r2as1.dd %f4,%f6,%f8 + + r2ast.ss %f3,%f4,%f5 + r2ast.sd %f7,%f8,%f9 + r2ast.dd %f6,%f8,%f10 + + i2s1.ss %f4,%f5,%f6 + i2s1.sd %f8,%f9,%f10 + i2s1.dd %f12,%f14,%f16 + + i2st.ss %f7,%f8,%f9 + i2st.sd %f11,%f12,%f13 + i2st.dd %f14,%f16,%f18 + + i2as1.ss %f10,%f11,%f12 + i2as1.sd %f14,%f15,%f16 + i2as1.dd %f16,%f18,%f20 + + i2ast.ss %f13,%f14,%f15 + i2ast.sd %f17,%f18,%f19 + i2ast.dd %f18,%f20,%f22 + + rat1s2.ss %f14,%f15,%f16 + rat1s2.sd %f20,%f21,%f22 + rat1s2.dd %f20,%f22,%f24 + + m12asm.ss %f15,%f16,%f17 + m12asm.sd %f23,%f24,%f25 + m12asm.dd %f22,%f24,%f26 + + ra1s2.ss %f18,%f19,%f20 + ra1s2.sd %f26,%f27,%f28 + ra1s2.dd %f20,%f22,%f24 + + m12ttsa.ss %f19,%f20,%f21 + m12ttsa.sd %f29,%f30,%f31 + m12ttsa.dd %f22,%f24,%f26 + + iat1s2.ss %f20,%f21,%f22 + iat1s2.sd %f0,%f1,%f2 + iat1s2.dd %f24,%f26,%f28 + + m12tsm.ss %f21,%f22,%f23 + m12tsm.sd %f3,%f4,%f5 + m12tsm.dd %f30,%f0,%f2 + + ia1s2.ss %f22,%f23,%f24 + ia1s2.sd %f6,%f7,%f8 + ia1s2.dd %f4,%f6,%f8 + + m12tsa.ss %f23,%f24,%f25 + m12tsa.sd %f9,%f10,%f11 + m12tsa.dd %f6,%f8,%f10 + + # pfsm with dual bit + d.r2s1.ss %f0,%f1,%f2 + nop + d.r2s1.sd %f3,%f4,%f5 + nop + d.r2s1.dd %f0,%f2,%f4 + nop + + d.r2st.ss %f1,%f2,%f3 + nop + d.r2st.sd %f4,%f5,%f6 + nop + d.r2st.dd %f2,%f4,%f6 + nop + + d.r2as1.ss %f2,%f3,%f4 + nop + d.r2as1.sd %f6,%f7,%f8 + nop + d.r2as1.dd %f4,%f6,%f8 + nop + + d.r2ast.ss %f3,%f4,%f5 + nop + d.r2ast.sd %f7,%f8,%f9 + nop + d.r2ast.dd %f6,%f8,%f10 + nop + + d.i2s1.ss %f4,%f5,%f6 + nop + d.i2s1.sd %f8,%f9,%f10 + nop + d.i2s1.dd %f12,%f14,%f16 + nop + + d.i2st.ss %f7,%f8,%f9 + nop + d.i2st.sd %f11,%f12,%f13 + nop + d.i2st.dd %f14,%f16,%f18 + nop + + d.i2as1.ss %f10,%f11,%f12 + nop + d.i2as1.sd %f14,%f15,%f16 + nop + d.i2as1.dd %f16,%f18,%f20 + nop + + d.i2ast.ss %f13,%f14,%f15 + nop + d.i2ast.sd %f17,%f18,%f19 + nop + d.i2ast.dd %f18,%f20,%f22 + nop + + d.rat1s2.ss %f14,%f15,%f16 + nop + d.rat1s2.sd %f20,%f21,%f22 + nop + d.rat1s2.dd %f20,%f22,%f24 + nop + + d.m12asm.ss %f15,%f16,%f17 + nop + d.m12asm.sd %f23,%f24,%f25 + nop + d.m12asm.dd %f22,%f24,%f26 + nop + + d.ra1s2.ss %f18,%f19,%f20 + nop + d.ra1s2.sd %f26,%f27,%f28 + nop + d.ra1s2.dd %f20,%f22,%f24 + nop + + d.m12ttsa.ss %f19,%f20,%f21 + nop + d.m12ttsa.sd %f29,%f30,%f31 + nop + d.m12ttsa.dd %f22,%f24,%f26 + nop + + d.iat1s2.ss %f20,%f21,%f22 + nop + d.iat1s2.sd %f0,%f1,%f2 + nop + d.iat1s2.dd %f24,%f26,%f28 + nop + + d.m12tsm.ss %f21,%f22,%f23 + nop + d.m12tsm.sd %f3,%f4,%f5 + nop + d.m12tsm.dd %f30,%f0,%f2 + nop + + d.ia1s2.ss %f22,%f23,%f24 + nop + d.ia1s2.sd %f6,%f7,%f8 + nop + d.ia1s2.dd %f4,%f6,%f8 + nop + + d.m12tsa.ss %f23,%f24,%f25 + nop + d.m12tsa.sd %f9,%f10,%f11 + nop + d.m12tsa.dd %f6,%f8,%f10 + nop + diff --git a/gas/testsuite/gas/i860/pic.d b/gas/testsuite/gas/i860/pic.d new file mode 100644 index 00000000000..d685e5a03dc --- /dev/null +++ b/gas/testsuite/gas/i860/pic.d @@ -0,0 +1,37 @@ +#as: +#objdump: -dr +#name: i860 PIC selectors + +.*: +file format .* + + +Disassembly of section \.text: + +00000000 : + 0: 01 00 00 6c call 0x00000008 // 8 + 4: 00 00 00 a0 shl %r0,%r0,%r0 + 8: 00 00 0f ec orh 0x0000,%r0,%r15 + 8: R_860_HAPC _GLOBAL_OFFSET_TABLE_ + c: 00 00 ef 95 adds 0,%r15,%r15 + c: R_860_LOPC _GLOBAL_OFFSET_TABLE_\+0x4 + 10: 00 08 ef 81 addu %r1,%r15,%r15 + 14: 00 00 1f ec orh 0x0000,%r0,%r31 + 14: R_860_HAGOT gsym + 18: 00 78 ff 83 addu %r15,%r31,%r31 + 1c: 01 00 f0 17 ld\.l 0\(%r31\),%r16 + 1c: R_860_LOGOT1 gsym + 20: 00 00 1f ec orh 0x0000,%r0,%r31 + 20: R_860_HIGOT gsym + 24: 00 00 ff e7 or 0x0000,%r31,%r31 + 24: R_860_LOGOT0 gsym + 28: 00 00 1f ec orh 0x0000,%r0,%r31 + 28: R_860_HIGOTOFF \.data + 2c: 00 00 ff e7 or 0x0000,%r31,%r31 + 2c: R_860_LOGOTOFF0 \.data + 30: 00 00 1f ec orh 0x0000,%r0,%r31 + 30: R_860_HAGOTOFF \.data\+0x8 + 34: 01 00 f0 17 ld\.l 0\(%r31\),%r16 + 34: R_860_LOGOTOFF1 \.data\+0x8 + 38: 00 00 00 6c call 0x0000003c // 3c + 38: R_860_PLT26 gsym + 3c: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/pic.s b/gas/testsuite/gas/i860/pic.s new file mode 100644 index 00000000000..09eec20da28 --- /dev/null +++ b/gas/testsuite/gas/i860/pic.s @@ -0,0 +1,23 @@ +# PIC selectors and the relocations they select. + .text +foo: + call 1f + nop +1: orh [_GLOBAL_OFFSET_TABLE_]@pc@ha,%r0,%r15 + adds [_GLOBAL_OFFSET_TABLE_+4]@pc@l,%r15,%r15 + addu %r1,%r15,%r15 + orh [gsym]@got@ha,%r0,%r31 + addu %r15,%r31,%r31 + ld.l [gsym]@got@l(%r31),%r16 + orh [gsym]@got@h,%r0,%r31 + or [gsym]@got@l,%r31,%r31 + orh [lsym]@gotoff@h,%r0,%r31 + or [lsym]@gotoff@l,%r31,%r31 + orh [lsym+8]@gotoff@ha,%r0,%r31 + ld.l [lsym+8]@gotoff@l(%r31),%r16 + call gsym@plt + nop + .data +lsym: .long 0 + .long 0 + .long 0 diff --git a/gas/testsuite/gas/i860/pseudo-ops01.d b/gas/testsuite/gas/i860/pseudo-ops01.d new file mode 100644 index 00000000000..3131e2efee4 --- /dev/null +++ b/gas/testsuite/gas/i860/pseudo-ops01.d @@ -0,0 +1,14 @@ +#as: +#objdump: -d +#name: i860 pseudo-ops01 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 49 28 06 48 fiadd\.ss %f5,%f0,%f6 + 4: c9 41 0a 48 fiadd\.dd %f8,%f0,%f10 + 8: b3 18 14 48 famov\.sd %f3,%f20 + c: 33 c1 09 48 famov\.ds %f24,%f9 + 10: 33 e5 03 48 pfamov\.ds %f28,%f3 diff --git a/gas/testsuite/gas/i860/pseudo-ops01.s b/gas/testsuite/gas/i860/pseudo-ops01.s new file mode 100644 index 00000000000..4b88925bd83 --- /dev/null +++ b/gas/testsuite/gas/i860/pseudo-ops01.s @@ -0,0 +1,10 @@ +# Test some assembler pseudo-operations: +# Floating point moves. + + .text + fmov.ss %f5,%f6 + fmov.dd %f8,%f10 + fmov.sd %f3,%f20 + fmov.ds %f24,%f9 + pfmov.ds %f28,%f3 + diff --git a/gas/testsuite/gas/i860/regress01.d b/gas/testsuite/gas/i860/regress01.d new file mode 100644 index 00000000000..1ddfa4b3cc7 --- /dev/null +++ b/gas/testsuite/gas/i860/regress01.d @@ -0,0 +1,21 @@ +#as: +#objdump: -dr +#name: i860 regress01 + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: f2 ff 50 2c fst.l %f16,-16\(%sp\) + 4: f2 ff 54 2c fst.l %f20,-16\(%sp\) + 8: f2 ff 58 2c fst.l %f24,-16\(%sp\) + c: f3 ff 50 2c fst.l %f16,-16\(%sp\)\+\+ + 10: f3 ff 54 2c fst.l %f20,-16\(%sp\)\+\+ + 14: f3 ff 58 2c fst.l %f24,-16\(%sp\)\+\+ + 18: f4 ff 50 2c fst.q %f16,-16\(%sp\) + 1c: f4 ff 54 2c fst.q %f20,-16\(%sp\) + 20: f4 ff 58 2c fst.q %f24,-16\(%sp\) + 24: f5 ff 50 2c fst.q %f16,-16\(%sp\)\+\+ + 28: f5 ff 54 2c fst.q %f20,-16\(%sp\)\+\+ + 2c: f5 ff 58 2c fst.q %f24,-16\(%sp\)\+\+ diff --git a/gas/testsuite/gas/i860/regress01.s b/gas/testsuite/gas/i860/regress01.s new file mode 100644 index 00000000000..002c3bdc467 --- /dev/null +++ b/gas/testsuite/gas/i860/regress01.s @@ -0,0 +1,19 @@ +# Test fst.* with and without auto-increment. + + .text + + fst.l %f16,-16(%sp) + fst.l %f20,-16(%sp) + fst.l %f24,-16(%sp) + + fst.l %f16,-16(%sp)++ + fst.l %f20,-16(%sp)++ + fst.l %f24,-16(%sp)++ + + fst.q %f16,-16(%sp) + fst.q %f20,-16(%sp) + fst.q %f24,-16(%sp) + + fst.q %f16,-16(%sp)++ + fst.q %f20,-16(%sp)++ + fst.q %f24,-16(%sp)++ diff --git a/gas/testsuite/gas/i860/shift.d b/gas/testsuite/gas/i860/shift.d new file mode 100644 index 00000000000..e48ba16cafb --- /dev/null +++ b/gas/testsuite/gas/i860/shift.d @@ -0,0 +1,86 @@ +#as: +#objdump: -dr +#name: i860 shift + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 22 a0 shl %r0,%r1,%sp + 4: 00 18 85 a0 shl %fp,%r4,%r5 + 8: 00 30 e8 a0 shl %r6,%r7,%r8 + c: 00 48 4b a1 shl %r9,%r10,%r11 + 10: 00 f8 ae a1 shl %r31,%r13,%r14 + 14: 00 78 11 a2 shl %r15,%r16,%r17 + 18: 00 90 74 a2 shl %r18,%r19,%r20 + 1c: 00 a8 d7 a2 shl %r21,%r22,%r23 + 20: 00 c0 3f a3 shl %r24,%r25,%r31 + 24: 00 d8 9d a3 shl %r27,%r28,%r29 + 28: 00 f0 e0 a3 shl %r30,%r31,%r0 + 2c: 00 00 22 a8 shr %r0,%r1,%sp + 30: 00 18 85 a8 shr %fp,%r4,%r5 + 34: 00 30 e8 a8 shr %r6,%r7,%r8 + 38: 00 48 4b a9 shr %r9,%r10,%r11 + 3c: 00 f8 ae a9 shr %r31,%r13,%r14 + 40: 00 78 11 aa shr %r15,%r16,%r17 + 44: 00 90 74 aa shr %r18,%r19,%r20 + 48: 00 a8 d7 aa shr %r21,%r22,%r23 + 4c: 00 c0 3f ab shr %r24,%r25,%r31 + 50: 00 d8 9d ab shr %r27,%r28,%r29 + 54: 00 f0 e0 ab shr %r30,%r31,%r0 + 58: 00 00 22 b8 shra %r0,%r1,%sp + 5c: 00 18 85 b8 shra %fp,%r4,%r5 + 60: 00 30 e8 b8 shra %r6,%r7,%r8 + 64: 00 48 4b b9 shra %r9,%r10,%r11 + 68: 00 f8 ae b9 shra %r31,%r13,%r14 + 6c: 00 78 11 ba shra %r15,%r16,%r17 + 70: 00 90 74 ba shra %r18,%r19,%r20 + 74: 00 a8 d7 ba shra %r21,%r22,%r23 + 78: 00 c0 3f bb shra %r24,%r25,%r31 + 7c: 00 d8 9d bb shra %r27,%r28,%r29 + 80: 00 f0 e0 bb shra %r30,%r31,%r0 + 84: 00 00 22 b0 shrd %r0,%r1,%sp + 88: 00 18 85 b0 shrd %fp,%r4,%r5 + 8c: 00 30 e8 b0 shrd %r6,%r7,%r8 + 90: 00 48 4b b1 shrd %r9,%r10,%r11 + 94: 00 f8 ae b1 shrd %r31,%r13,%r14 + 98: 00 78 11 b2 shrd %r15,%r16,%r17 + 9c: 00 90 74 b2 shrd %r18,%r19,%r20 + a0: 00 a8 d7 b2 shrd %r21,%r22,%r23 + a4: 00 c0 3f b3 shrd %r24,%r25,%r31 + a8: 00 d8 9d b3 shrd %r27,%r28,%r29 + ac: 00 f0 e0 b3 shrd %r30,%r31,%r0 + b0: 00 00 22 a4 shl 0,%r1,%sp + b4: 00 20 85 a4 shl 8192,%r4,%r5 + b8: f5 13 e8 a4 shl 5109,%r7,%r8 + bc: ff 7f 4b a5 shl 32767,%r10,%r11 + c0: 00 80 ae a5 shl -32768,%r13,%r14 + c4: 00 e0 11 a6 shl -8192,%r16,%r17 + c8: ff ff 74 a6 shl -1,%r19,%r20 + cc: cd ab d7 a6 shl -21555,%r22,%r23 + d0: 34 12 3a a7 shl 4660,%r25,%r26 + d4: 00 00 9d a7 shl 0,%r28,%r29 + d8: 03 00 e0 a7 shl 3,%r31,%r0 + dc: 00 00 22 ac shr 0,%r1,%sp + e0: 00 20 85 ac shr 8192,%r4,%r5 + e4: f5 13 e8 ac shr 5109,%r7,%r8 + e8: ff 7f 4b ad shr 32767,%r10,%r11 + ec: 00 80 ae ad shr -32768,%r13,%r14 + f0: 00 e0 11 ae shr -8192,%r16,%r17 + f4: ff ff 74 ae shr -1,%r19,%r20 + f8: cd ab d7 ae shr -21555,%r22,%r23 + fc: 34 12 3a af shr 4660,%r25,%r26 + 100: 00 00 9d af shr 0,%r28,%r29 + 104: 03 00 e0 af shr 3,%r31,%r0 + 108: 01 00 22 bc shra 1,%r1,%sp + 10c: 01 20 85 bc shra 8193,%r4,%r5 + 110: f6 13 e8 bc shra 5110,%r7,%r8 + 114: ff 7f 4b bd shra 32767,%r10,%r11 + 118: 00 80 ae bd shra -32768,%r13,%r14 + 11c: 00 e0 11 be shra -8192,%r16,%r17 + 120: ff ff 74 be shra -1,%r19,%r20 + 124: cd ab d7 be shra -21555,%r22,%r23 + 128: 34 12 3a bf shra 4660,%r25,%r26 + 12c: 00 00 9d bf shra 0,%r28,%r29 + 130: 03 00 e0 bf shra 3,%r31,%r0 diff --git a/gas/testsuite/gas/i860/shift.s b/gas/testsuite/gas/i860/shift.s new file mode 100644 index 00000000000..0d0d1896539 --- /dev/null +++ b/gas/testsuite/gas/i860/shift.s @@ -0,0 +1,90 @@ +# shl, shr, shra, shrd + + .text + + # Register forms (all) + shl %r0,%r1,%r2 + shl %r3,%r4,%r5 + shl %r6,%r7,%r8 + shl %r9,%r10,%r11 + shl %r31,%r13,%r14 + shl %r15,%r16,%r17 + shl %r18,%r19,%r20 + shl %r21,%r22,%r23 + shl %r24,%r25,%r31 + shl %r27,%r28,%r29 + shl %r30,%r31,%r0 + + shr %r0,%r1,%r2 + shr %r3,%r4,%r5 + shr %r6,%r7,%r8 + shr %r9,%r10,%r11 + shr %r31,%r13,%r14 + shr %r15,%r16,%r17 + shr %r18,%r19,%r20 + shr %r21,%r22,%r23 + shr %r24,%r25,%r31 + shr %r27,%r28,%r29 + shr %r30,%r31,%r0 + + shra %r0,%r1,%r2 + shra %r3,%r4,%r5 + shra %r6,%r7,%r8 + shra %r9,%r10,%r11 + shra %r31,%r13,%r14 + shra %r15,%r16,%r17 + shra %r18,%r19,%r20 + shra %r21,%r22,%r23 + shra %r24,%r25,%r31 + shra %r27,%r28,%r29 + shra %r30,%r31,%r0 + + shrd %r0,%r1,%r2 + shrd %r3,%r4,%r5 + shrd %r6,%r7,%r8 + shrd %r9,%r10,%r11 + shrd %r31,%r13,%r14 + shrd %r15,%r16,%r17 + shrd %r18,%r19,%r20 + shrd %r21,%r22,%r23 + shrd %r24,%r25,%r31 + shrd %r27,%r28,%r29 + shrd %r30,%r31,%r0 + + # Immediate forms (shrd does not have an immediate form) + shl 0,%r1,%r2 + shl 8192,%r4,%r5 + shl 5109,%r7,%r8 + shl 32767,%r10,%r11 + shl -32768,%r13,%r14 + shl -8192,%r16,%r17 + shl -1,%r19,%r20 + shl -21555,%r22,%r23 + shl 0x1234,%r25,%r26 + shl 0x0,%r28,%r29 + shl 0x3,%r31,%r0 + + shr 0,%r1,%r2 + shr 8192,%r4,%r5 + shr 5109,%r7,%r8 + shr 32767,%r10,%r11 + shr -32768,%r13,%r14 + shr -8192,%r16,%r17 + shr -1,%r19,%r20 + shr -21555,%r22,%r23 + shr 0x1234,%r25,%r26 + shr 0x0,%r28,%r29 + shr 0x3,%r31,%r0 + + shra 1,%r1,%r2 + shra 8193,%r4,%r5 + shra 5110,%r7,%r8 + shra 32767,%r10,%r11 + shra -32768,%r13,%r14 + shra -8192,%r16,%r17 + shra -1,%r19,%r20 + shra -21555,%r22,%r23 + shra 0x1234,%r25,%r26 + shra 0x0,%r28,%r29 + shra 0x3,%r31,%r0 + diff --git a/gas/testsuite/gas/i860/simd.d b/gas/testsuite/gas/i860/simd.d new file mode 100644 index 00000000000..288519605b3 --- /dev/null +++ b/gas/testsuite/gas/i860/simd.d @@ -0,0 +1,105 @@ +#as: +#objdump: -dr +#name: i860 simd + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: d7 05 48 48 pfzchkl %f0,%f2,%f8 + 4: d7 15 90 48 pfzchkl %f2,%f4,%f16 + 8: d7 25 cd 48 pfzchkl %f4,%f6,%f13 + c: d7 45 52 49 pfzchkl %f8,%f10,%f18 + 10: df 65 de 49 pfzchks %f12,%f14,%f30 + 14: df 85 54 4a pfzchks %f16,%f18,%f20 + 18: df a5 dc 4a pfzchks %f20,%f22,%f28 + 1c: df c5 5e 4b pfzchks %f24,%f26,%f30 + 20: d0 05 48 48 pfaddp %f0,%f2,%f8 + 24: d0 15 90 48 pfaddp %f2,%f4,%f16 + 28: d0 25 cd 48 pfaddp %f4,%f6,%f13 + 2c: d0 45 52 49 pfaddp %f8,%f10,%f18 + 30: d1 65 de 49 pfaddz %f12,%f14,%f30 + 34: d1 85 54 4a pfaddz %f16,%f18,%f20 + 38: d1 a5 dc 4a pfaddz %f20,%f22,%f28 + 3c: d1 c5 5e 4b pfaddz %f24,%f26,%f30 + 40: d7 61 44 48 fzchkl %f12,%f2,%f4 + 44: d7 b1 82 48 fzchkl %f22,%f4,%f2 + 48: d7 21 d2 48 fzchkl %f4,%f6,%f18 + 4c: d7 41 5c 49 fzchkl %f8,%f10,%f28 + 50: df 61 c6 49 fzchks %f12,%f14,%f6 + 54: df 81 54 4a fzchks %f16,%f18,%f20 + 58: df a1 dc 4a fzchks %f20,%f22,%f28 + 5c: df c1 5e 4b fzchks %f24,%f26,%f30 + 60: d0 61 44 48 faddp %f12,%f2,%f4 + 64: d0 b1 82 48 faddp %f22,%f4,%f2 + 68: d0 21 d2 48 faddp %f4,%f6,%f18 + 6c: d0 41 5c 49 faddp %f8,%f10,%f28 + 70: d1 61 c6 49 faddz %f12,%f14,%f6 + 74: d1 81 54 4a faddz %f16,%f18,%f20 + 78: d1 a1 dc 4a faddz %f20,%f22,%f28 + 7c: d1 c1 5e 4b faddz %f24,%f26,%f30 + 80: d7 07 52 48 d.pfzchkl %f0,%f2,%f18 + 84: 00 00 00 a0 shl %r0,%r0,%r0 + 88: d7 17 8c 48 d.pfzchkl %f2,%f4,%f12 + 8c: 00 00 00 a0 shl %r0,%r0,%r0 + 90: d7 27 de 48 d.pfzchkl %f4,%f6,%f30 + 94: 00 00 00 a0 shl %r0,%r0,%r0 + 98: d7 47 44 49 d.pfzchkl %f8,%f10,%f4 + 9c: 00 00 00 a0 shl %r0,%r0,%r0 + a0: df 67 ce 49 d.pfzchks %f12,%f14,%f14 + a4: 00 00 00 a0 shl %r0,%r0,%r0 + a8: df 87 46 4a d.pfzchks %f16,%f18,%f6 + ac: 00 00 00 a0 shl %r0,%r0,%r0 + b0: df a7 ca 4a d.pfzchks %f20,%f22,%f10 + b4: 00 00 00 a0 shl %r0,%r0,%r0 + b8: df c7 48 4b d.pfzchks %f24,%f26,%f8 + bc: 00 00 00 a0 shl %r0,%r0,%r0 + c0: d0 07 52 48 d.pfaddp %f0,%f2,%f18 + c4: 00 00 00 a0 shl %r0,%r0,%r0 + c8: d0 17 80 48 d.pfaddp %f2,%f4,%f0 + cc: 00 00 00 a0 shl %r0,%r0,%r0 + d0: d0 27 de 48 d.pfaddp %f4,%f6,%f30 + d4: 00 00 00 a0 shl %r0,%r0,%r0 + d8: d0 47 44 49 d.pfaddp %f8,%f10,%f4 + dc: 00 00 00 a0 shl %r0,%r0,%r0 + e0: d1 67 ce 49 d.pfaddz %f12,%f14,%f14 + e4: 00 00 00 a0 shl %r0,%r0,%r0 + e8: d1 87 46 4a d.pfaddz %f16,%f18,%f6 + ec: 00 00 00 a0 shl %r0,%r0,%r0 + f0: d1 a7 ca 4a d.pfaddz %f20,%f22,%f10 + f4: 00 00 00 a0 shl %r0,%r0,%r0 + f8: d1 c7 48 4b d.pfaddz %f24,%f26,%f8 + fc: 00 00 00 a0 shl %r0,%r0,%r0 + 100: d7 03 4a 48 d.fzchkl %f0,%f2,%f10 + 104: 00 00 00 a0 shl %r0,%r0,%r0 + 108: d7 13 92 48 d.fzchkl %f2,%f4,%f18 + 10c: 00 00 00 a0 shl %r0,%r0,%r0 + 110: d7 23 cc 48 d.fzchkl %f4,%f6,%f12 + 114: 00 00 00 a0 shl %r0,%r0,%r0 + 118: d7 43 4e 49 d.fzchkl %f8,%f10,%f14 + 11c: 00 00 00 a0 shl %r0,%r0,%r0 + 120: df 63 d0 49 d.fzchks %f12,%f14,%f16 + 124: 00 00 00 a0 shl %r0,%r0,%r0 + 128: df 83 4c 4a d.fzchks %f16,%f18,%f12 + 12c: 00 00 00 a0 shl %r0,%r0,%r0 + 130: df a3 d0 4a d.fzchks %f20,%f22,%f16 + 134: 00 00 00 a0 shl %r0,%r0,%r0 + 138: df c3 5e 4b d.fzchks %f24,%f26,%f30 + 13c: 00 00 00 a0 shl %r0,%r0,%r0 + 140: d0 03 4a 48 d.faddp %f0,%f2,%f10 + 144: 00 00 00 a0 shl %r0,%r0,%r0 + 148: d0 13 92 48 d.faddp %f2,%f4,%f18 + 14c: 00 00 00 a0 shl %r0,%r0,%r0 + 150: d0 23 cc 48 d.faddp %f4,%f6,%f12 + 154: 00 00 00 a0 shl %r0,%r0,%r0 + 158: d0 43 4e 49 d.faddp %f8,%f10,%f14 + 15c: 00 00 00 a0 shl %r0,%r0,%r0 + 160: d1 63 d0 49 d.faddz %f12,%f14,%f16 + 164: 00 00 00 a0 shl %r0,%r0,%r0 + 168: d1 83 4c 4a d.faddz %f16,%f18,%f12 + 16c: 00 00 00 a0 shl %r0,%r0,%r0 + 170: d1 a3 d0 4a d.faddz %f20,%f22,%f16 + 174: 00 00 00 a0 shl %r0,%r0,%r0 + 178: d1 c3 5e 4b d.faddz %f24,%f26,%f30 + 17c: 00 00 00 a0 shl %r0,%r0,%r0 diff --git a/gas/testsuite/gas/i860/simd.s b/gas/testsuite/gas/i860/simd.s new file mode 100644 index 00000000000..4f252dd1bf5 --- /dev/null +++ b/gas/testsuite/gas/i860/simd.s @@ -0,0 +1,119 @@ +# fzchkl, fzchks, faddp, faddz + + .text + + # Pipelined, without dual bit + pfzchkl %f0,%f2,%f8 + pfzchkl %f2,%f4,%f16 + pfzchkl %f4,%f6,%f13 + pfzchkl %f8,%f10,%f18 + + pfzchks %f12,%f14,%f30 + pfzchks %f16,%f18,%f20 + pfzchks %f20,%f22,%f28 + pfzchks %f24,%f26,%f30 + + pfaddp %f0,%f2,%f8 + pfaddp %f2,%f4,%f16 + pfaddp %f4,%f6,%f13 + pfaddp %f8,%f10,%f18 + + pfaddz %f12,%f14,%f30 + pfaddz %f16,%f18,%f20 + pfaddz %f20,%f22,%f28 + pfaddz %f24,%f26,%f30 + + # Non-pipelined, without dual bit + fzchkl %f12,%f2,%f4 + fzchkl %f22,%f4,%f2 + fzchkl %f4,%f6,%f18 + fzchkl %f8,%f10,%f28 + + fzchks %f12,%f14,%f6 + fzchks %f16,%f18,%f20 + fzchks %f20,%f22,%f28 + fzchks %f24,%f26,%f30 + + faddp %f12,%f2,%f4 + faddp %f22,%f4,%f2 + faddp %f4,%f6,%f18 + faddp %f8,%f10,%f28 + + faddz %f12,%f14,%f6 + faddz %f16,%f18,%f20 + faddz %f20,%f22,%f28 + faddz %f24,%f26,%f30 + + # Pipelined, with dual bit + d.pfzchkl %f0,%f2,%f18 + nop + d.pfzchkl %f2,%f4,%f12 + nop + d.pfzchkl %f4,%f6,%f30 + nop + d.pfzchkl %f8,%f10,%f4 + nop + + d.pfzchks %f12,%f14,%f14 + nop + d.pfzchks %f16,%f18,%f6 + nop + d.pfzchks %f20,%f22,%f10 + nop + d.pfzchks %f24,%f26,%f8 + nop + + d.pfaddp %f0,%f2,%f18 + nop + d.pfaddp %f2,%f4,%f0 + nop + d.pfaddp %f4,%f6,%f30 + nop + d.pfaddp %f8,%f10,%f4 + nop + + d.pfaddz %f12,%f14,%f14 + nop + d.pfaddz %f16,%f18,%f6 + nop + d.pfaddz %f20,%f22,%f10 + nop + d.pfaddz %f24,%f26,%f8 + nop + + # Non-pipelined, with dual bit + d.fzchkl %f0,%f2,%f10 + nop + d.fzchkl %f2,%f4,%f18 + nop + d.fzchkl %f4,%f6,%f12 + nop + d.fzchkl %f8,%f10,%f14 + nop + + d.fzchks %f12,%f14,%f16 + nop + d.fzchks %f16,%f18,%f12 + nop + d.fzchks %f20,%f22,%f16 + nop + d.fzchks %f24,%f26,%f30 + nop + + d.faddp %f0,%f2,%f10 + nop + d.faddp %f2,%f4,%f18 + nop + d.faddp %f4,%f6,%f12 + nop + d.faddp %f8,%f10,%f14 + nop + + d.faddz %f12,%f14,%f16 + nop + d.faddz %f16,%f18,%f12 + nop + d.faddz %f20,%f22,%f16 + nop + d.faddz %f24,%f26,%f30 + nop diff --git a/gas/testsuite/gas/i860/system.d b/gas/testsuite/gas/i860/system.d new file mode 100644 index 00000000000..a7979611acb --- /dev/null +++ b/gas/testsuite/gas/i860/system.d @@ -0,0 +1,72 @@ +#as: +#objdump: -dr +#name: i860 system + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 01 00 00 4c lock + 4: 07 00 00 4c unlock + 8: 04 00 00 4c intovr + c: 00 00 00 44 trap %r0,%r0,%r0 + 10: 00 f8 ff 47 trap %r31,%r31,%r31 + 14: 00 08 b2 44 trap %r1,%r5,%r18 + 18: 00 f8 86 46 trap %r31,%r20,%r6 + 1c: 00 00 01 30 ld.c %fir,%r1 + 20: 00 00 1f 30 ld.c %fir,%r31 + 24: 00 00 25 30 ld.c %psr,%r5 + 28: 00 00 3e 30 ld.c %psr,%r30 + 2c: 00 00 4a 30 ld.c %dirbase,%r10 + 30: 00 00 42 30 ld.c %dirbase,%sp + 34: 00 00 75 30 ld.c %db,%r21 + 38: 00 00 60 30 ld.c %db,%r0 + 3c: 00 00 9c 30 ld.c %fsr,%r28 + 40: 00 00 8c 30 ld.c %fsr,%r12 + 44: 00 00 bf 30 ld.c %epsr,%r31 + 48: 00 00 a6 30 ld.c %epsr,%r6 + 4c: 00 00 00 38 st.c %r0,%fir + 50: 00 f0 00 38 st.c %r30,%fir + 54: 00 38 20 38 st.c %r7,%psr + 58: 00 f8 20 38 st.c %r31,%psr + 5c: 00 58 40 38 st.c %r11,%dirbase + 60: 00 18 40 38 st.c %fp,%dirbase + 64: 00 b0 60 38 st.c %r22,%db + 68: 00 78 60 38 st.c %r15,%db + 6c: 00 e8 80 38 st.c %r29,%fsr + 70: 00 68 80 38 st.c %r13,%fsr + 74: 00 20 a0 38 st.c %r4,%epsr + 78: 00 30 a0 38 st.c %r6,%epsr + 7c: 04 00 00 34 flush 0\(%r0\) + 80: 84 00 20 34 flush 128\(%r1\) + 84: 04 01 40 34 flush 256\(%sp\) + 88: 04 02 60 34 flush 512\(%fp\) + 8c: 04 04 80 34 flush 1024\(%r4\) + 90: 04 10 a0 34 flush 4096\(%r5\) + 94: 04 20 c0 34 flush 8192\(%r6\) + 98: 04 40 e0 34 flush 16384\(%r7\) + 9c: 04 c0 00 35 flush -16384\(%r8\) + a0: 04 e0 20 35 flush -8192\(%r9\) + a4: 04 f0 40 35 flush -4096\(%r10\) + a8: 04 fc 60 35 flush -1024\(%r11\) + ac: 04 fe 80 35 flush -512\(%r12\) + b0: 0c ff a0 35 flush -248\(%r13\) + b4: e4 ff c0 35 flush -32\(%r14\) + b8: f4 ff c0 35 flush -16\(%r14\) + bc: 05 00 00 34 flush 0\(%r0\)\+\+ + c0: 85 00 20 34 flush 128\(%r1\)\+\+ + c4: 05 01 40 34 flush 256\(%sp\)\+\+ + c8: 05 02 60 34 flush 512\(%fp\)\+\+ + cc: 05 04 80 34 flush 1024\(%r4\)\+\+ + d0: 05 10 c0 36 flush 4096\(%r22\)\+\+ + d4: 05 20 e0 36 flush 8192\(%r23\)\+\+ + d8: 05 40 00 37 flush 16384\(%r24\)\+\+ + dc: 05 c0 20 37 flush -16384\(%r25\)\+\+ + e0: 05 e0 40 37 flush -8192\(%r26\)\+\+ + e4: 05 f0 60 37 flush -4096\(%r27\)\+\+ + e8: 05 fc 80 37 flush -1024\(%r28\)\+\+ + ec: 05 fe a0 37 flush -512\(%r29\)\+\+ + f0: 0d ff c0 37 flush -248\(%r30\)\+\+ + f4: 25 00 e0 37 flush 32\(%r31\)\+\+ + f8: 15 00 e0 37 flush 16\(%r31\)\+\+ diff --git a/gas/testsuite/gas/i860/system.s b/gas/testsuite/gas/i860/system.s new file mode 100644 index 00000000000..62bcbfcfcb2 --- /dev/null +++ b/gas/testsuite/gas/i860/system.s @@ -0,0 +1,76 @@ +# System and privileged instructions +# ld.c, st.c, flush, lock, unlock, intovr, trap + + .text + + lock + unlock + intovr + + trap %r0,%r0,%r0 + trap %r31,%r31,%r31 + trap %r1,%r5,%r18 + trap %r31,%r20,%r6 + + ld.c %fir,%r1 + ld.c %fir,%r31 + ld.c %psr,%r5 + ld.c %psr,%r30 + ld.c %dirbase,%r10 + ld.c %dirbase,%r2 + ld.c %db,%r21 + ld.c %db,%r0 + ld.c %fsr,%r28 + ld.c %fsr,%r12 + ld.c %epsr,%r31 + ld.c %epsr,%r6 + + st.c %r0,%fir + st.c %r30,%fir + st.c %r7,%psr + st.c %r31,%psr + st.c %r11,%dirbase + st.c %r3,%dirbase + st.c %r22,%db + st.c %r15,%db + st.c %r29,%fsr + st.c %r13,%fsr + st.c %r4,%epsr + st.c %r6,%epsr + + # Flush, no auto-increment. + flush 0(%r0) + flush 128(%r1) + flush 256(%r2) + flush 512(%r3) + flush 1024(%r4) + flush 4096(%r5) + flush 8192(%r6) + flush 16384(%r7) + flush -16384(%r8) + flush -8192(%r9) + flush -4096(%r10) + flush -1024(%r11) + flush -512(%r12) + flush -248(%r13) + flush -32(%r14) + flush -16(%r14) + + # Flush, auto-increment. + flush 0(%r0)++ + flush 128(%r1)++ + flush 256(%r2)++ + flush 512(%r3)++ + flush 1024(%r4)++ + flush 4096(%r22)++ + flush 8192(%r23)++ + flush 16384(%r24)++ + flush -16384(%r25)++ + flush -8192(%r26)++ + flush -4096(%r27)++ + flush -1024(%r28)++ + flush -512(%r29)++ + flush -248(%r30)++ + flush 32(%r31)++ + flush 16(%r31)++ + diff --git a/gas/testsuite/gas/i860/xp.d b/gas/testsuite/gas/i860/xp.d new file mode 100644 index 00000000000..6dad9979886 --- /dev/null +++ b/gas/testsuite/gas/i860/xp.d @@ -0,0 +1,241 @@ +#as: -mxp +#objdump: -dr +#name: i860 xp (XP-only instructions) + +.*: +file format .* + +Disassembly of section \.text: + +00000000 <\.text>: + 0: 00 00 df 30 ld.c %bear,%r31 + 4: 00 00 c0 30 ld.c %bear,%r0 + 8: 00 00 e5 30 ld.c %ccr,%r5 + c: 00 00 fe 30 ld.c %ccr,%r30 + 10: 00 00 0a 31 ld.c %p0,%r10 + 14: 00 00 02 31 ld.c %p0,%sp + 18: 00 00 35 31 ld.c %p1,%r21 + 1c: 00 00 20 31 ld.c %p1,%r0 + 20: 00 00 5c 31 ld.c %p2,%r28 + 24: 00 00 4c 31 ld.c %p2,%r12 + 28: 00 00 7f 31 ld.c %p3,%r31 + 2c: 00 00 66 31 ld.c %p3,%r6 + 30: 00 00 c0 38 st.c %r0,%bear + 34: 00 f0 c0 38 st.c %r30,%bear + 38: 00 38 e0 38 st.c %r7,%ccr + 3c: 00 f8 e0 38 st.c %r31,%ccr + 40: 00 58 00 39 st.c %r11,%p0 + 44: 00 18 00 39 st.c %fp,%p0 + 48: 00 b0 20 39 st.c %r22,%p1 + 4c: 00 78 20 39 st.c %r15,%p1 + 50: 00 e8 40 39 st.c %r29,%p2 + 54: 00 68 40 39 st.c %r13,%p2 + 58: 00 20 60 39 st.c %r4,%p3 + 5c: 00 30 60 39 st.c %r6,%p3 + 60: 0a 04 05 4c ldint.l %r0,%r5 + 64: 0a 04 df 4c ldint.l %r6,%r31 + 68: 0a 04 fe 4c ldint.l %r7,%r30 + 6c: 0a 04 1d 4d ldint.l %r8,%r29 + 70: 0a 04 3c 4d ldint.l %r9,%r28 + 74: 0a 04 1b 4c ldint.l %r0,%r27 + 78: 0a 04 3a 4c ldint.l %r1,%r26 + 7c: 0a 04 99 4d ldint.l %r12,%r25 + 80: 0a 04 b8 4d ldint.l %r13,%r24 + 84: 0a 04 d7 4d ldint.l %r14,%r23 + 88: 0a 04 f6 4d ldint.l %r15,%r22 + 8c: 0a 04 15 4e ldint.l %r16,%r21 + 90: 0a 04 34 4e ldint.l %r17,%r20 + 94: 0a 04 93 4f ldint.l %r28,%r19 + 98: 0a 04 f2 4f ldint.l %r31,%r18 + 9c: 0a 02 05 4c ldint.s %r0,%r5 + a0: 0a 02 df 4c ldint.s %r6,%r31 + a4: 0a 02 fe 4c ldint.s %r7,%r30 + a8: 0a 02 1d 4d ldint.s %r8,%r29 + ac: 0a 02 3c 4d ldint.s %r9,%r28 + b0: 0a 02 1b 4c ldint.s %r0,%r27 + b4: 0a 02 3a 4c ldint.s %r1,%r26 + b8: 0a 02 99 4d ldint.s %r12,%r25 + bc: 0a 02 b8 4d ldint.s %r13,%r24 + c0: 0a 02 d7 4d ldint.s %r14,%r23 + c4: 0a 02 f6 4d ldint.s %r15,%r22 + c8: 0a 02 15 4e ldint.s %r16,%r21 + cc: 0a 02 34 4e ldint.s %r17,%r20 + d0: 0a 02 93 4f ldint.s %r28,%r19 + d4: 0a 02 f2 4f ldint.s %r31,%r18 + d8: 0a 00 05 4c ldint.b %r0,%r5 + dc: 0a 00 df 4c ldint.b %r6,%r31 + e0: 0a 00 fe 4c ldint.b %r7,%r30 + e4: 0a 00 1d 4d ldint.b %r8,%r29 + e8: 0a 00 3c 4d ldint.b %r9,%r28 + ec: 0a 00 1b 4c ldint.b %r0,%r27 + f0: 0a 00 3a 4c ldint.b %r1,%r26 + f4: 0a 00 99 4d ldint.b %r12,%r25 + f8: 0a 00 b8 4d ldint.b %r13,%r24 + fc: 0a 00 d7 4d ldint.b %r14,%r23 + 100: 0a 00 f6 4d ldint.b %r15,%r22 + 104: 0a 00 15 4e ldint.b %r16,%r21 + 108: 0a 00 34 4e ldint.b %r17,%r20 + 10c: 0a 00 93 4f ldint.b %r28,%r19 + 110: 0a 00 f2 4f ldint.b %r31,%r18 + 114: 08 04 05 4c ldio.l %r0,%r5 + 118: 08 04 df 4c ldio.l %r6,%r31 + 11c: 08 04 fe 4c ldio.l %r7,%r30 + 120: 08 04 1d 4d ldio.l %r8,%r29 + 124: 08 04 3c 4d ldio.l %r9,%r28 + 128: 08 04 1b 4c ldio.l %r0,%r27 + 12c: 08 04 3a 4c ldio.l %r1,%r26 + 130: 08 04 99 4d ldio.l %r12,%r25 + 134: 08 04 b8 4d ldio.l %r13,%r24 + 138: 08 04 d7 4d ldio.l %r14,%r23 + 13c: 08 04 f6 4d ldio.l %r15,%r22 + 140: 08 04 15 4e ldio.l %r16,%r21 + 144: 08 04 34 4e ldio.l %r17,%r20 + 148: 08 04 93 4f ldio.l %r28,%r19 + 14c: 08 04 f2 4f ldio.l %r31,%r18 + 150: 08 02 05 4c ldio.s %r0,%r5 + 154: 08 02 df 4c ldio.s %r6,%r31 + 158: 08 02 fe 4c ldio.s %r7,%r30 + 15c: 08 02 1d 4d ldio.s %r8,%r29 + 160: 08 02 3c 4d ldio.s %r9,%r28 + 164: 08 02 1b 4c ldio.s %r0,%r27 + 168: 08 02 3a 4c ldio.s %r1,%r26 + 16c: 08 02 99 4d ldio.s %r12,%r25 + 170: 08 02 b8 4d ldio.s %r13,%r24 + 174: 08 02 d7 4d ldio.s %r14,%r23 + 178: 08 02 f6 4d ldio.s %r15,%r22 + 17c: 08 02 15 4e ldio.s %r16,%r21 + 180: 08 02 34 4e ldio.s %r17,%r20 + 184: 08 02 93 4f ldio.s %r28,%r19 + 188: 08 02 f2 4f ldio.s %r31,%r18 + 18c: 08 00 05 4c ldio.b %r0,%r5 + 190: 08 00 df 4c ldio.b %r6,%r31 + 194: 08 00 fe 4c ldio.b %r7,%r30 + 198: 08 00 1d 4d ldio.b %r8,%r29 + 19c: 08 00 3c 4d ldio.b %r9,%r28 + 1a0: 08 00 1b 4c ldio.b %r0,%r27 + 1a4: 08 00 3a 4c ldio.b %r1,%r26 + 1a8: 08 00 99 4d ldio.b %r12,%r25 + 1ac: 08 00 b8 4d ldio.b %r13,%r24 + 1b0: 08 00 d7 4d ldio.b %r14,%r23 + 1b4: 08 00 f6 4d ldio.b %r15,%r22 + 1b8: 08 00 15 4e ldio.b %r16,%r21 + 1bc: 08 00 34 4e ldio.b %r17,%r20 + 1c0: 08 00 93 4f ldio.b %r28,%r19 + 1c4: 08 00 f2 4f ldio.b %r31,%r18 + 1c8: 09 04 a0 4c stio.l %r0,%r5 + 1cc: 09 34 e0 4f stio.l %r6,%r31 + 1d0: 09 3c c0 4f stio.l %r7,%r30 + 1d4: 09 44 a0 4f stio.l %r8,%r29 + 1d8: 09 4c 80 4f stio.l %r9,%r28 + 1dc: 09 04 60 4f stio.l %r0,%r27 + 1e0: 09 0c 40 4f stio.l %r1,%r26 + 1e4: 09 64 20 4f stio.l %r12,%r25 + 1e8: 09 6c 00 4f stio.l %r13,%r24 + 1ec: 09 74 e0 4e stio.l %r14,%r23 + 1f0: 09 7c c0 4e stio.l %r15,%r22 + 1f4: 09 84 a0 4e stio.l %r16,%r21 + 1f8: 09 8c 80 4e stio.l %r17,%r20 + 1fc: 09 e4 60 4e stio.l %r28,%r19 + 200: 09 fc 40 4e stio.l %r31,%r18 + 204: 09 02 a0 4c stio.s %r0,%r5 + 208: 09 32 e0 4f stio.s %r6,%r31 + 20c: 09 3a c0 4f stio.s %r7,%r30 + 210: 09 42 a0 4f stio.s %r8,%r29 + 214: 09 4a 80 4f stio.s %r9,%r28 + 218: 09 02 60 4f stio.s %r0,%r27 + 21c: 09 0a 40 4f stio.s %r1,%r26 + 220: 09 62 20 4f stio.s %r12,%r25 + 224: 09 6a 00 4f stio.s %r13,%r24 + 228: 09 72 e0 4e stio.s %r14,%r23 + 22c: 09 7a c0 4e stio.s %r15,%r22 + 230: 09 82 a0 4e stio.s %r16,%r21 + 234: 09 8a 80 4e stio.s %r17,%r20 + 238: 09 e2 60 4e stio.s %r28,%r19 + 23c: 09 fa 40 4e stio.s %r31,%r18 + 240: 09 00 a0 4c stio.b %r0,%r5 + 244: 09 30 e0 4f stio.b %r6,%r31 + 248: 09 38 c0 4f stio.b %r7,%r30 + 24c: 09 40 a0 4f stio.b %r8,%r29 + 250: 09 48 80 4f stio.b %r9,%r28 + 254: 09 00 60 4f stio.b %r0,%r27 + 258: 09 08 40 4f stio.b %r1,%r26 + 25c: 09 60 20 4f stio.b %r12,%r25 + 260: 09 68 00 4f stio.b %r13,%r24 + 264: 09 70 e0 4e stio.b %r14,%r23 + 268: 09 78 c0 4e stio.b %r15,%r22 + 26c: 09 80 a0 4e stio.b %r16,%r21 + 270: 09 88 80 4e stio.b %r17,%r20 + 274: 09 e0 60 4e stio.b %r28,%r19 + 278: 09 f8 40 4e stio.b %r31,%r18 + 27c: 0b 00 00 4c scyc.b %r0 + 280: 0b 00 a0 4c scyc.b %r5 + 284: 0b 00 c0 4c scyc.b %r6 + 288: 0b 00 a0 4d scyc.b %r13 + 28c: 0b 00 c0 4d scyc.b %r14 + 290: 0b 00 80 4f scyc.b %r28 + 294: 0b 00 a0 4f scyc.b %r29 + 298: 0b 00 c0 4f scyc.b %r30 + 29c: 0b 00 e0 4f scyc.b %r31 + 2a0: 04 00 00 64 pfld.q 0\(%r0\),%f0 + 2a4: 84 00 3c 64 pfld.q 128\(%r1\),%f28 + 2a8: 04 01 58 64 pfld.q 256\(%sp\),%f24 + 2ac: 04 02 74 64 pfld.q 512\(%fp\),%f20 + 2b0: 04 04 90 64 pfld.q 1024\(%r4\),%f16 + 2b4: 04 10 ac 64 pfld.q 4096\(%r5\),%f12 + 2b8: 04 20 c8 64 pfld.q 8192\(%r6\),%f8 + 2bc: 04 40 e4 64 pfld.q 16384\(%r7\),%f4 + 2c0: fc 7f e0 64 pfld.q 32760\(%r7\),%f0 + 2c4: 04 80 fc 64 pfld.q -32768\(%r7\),%f28 + 2c8: 04 c0 18 65 pfld.q -16384\(%r8\),%f24 + 2cc: 04 e0 34 65 pfld.q -8192\(%r9\),%f20 + 2d0: 04 f0 50 65 pfld.q -4096\(%r10\),%f16 + 2d4: 04 fc 6c 65 pfld.q -1024\(%r11\),%f12 + 2d8: 04 fe 88 65 pfld.q -512\(%r12\),%f8 + 2dc: 0c ff a4 65 pfld.q -248\(%r13\),%f4 + 2e0: fc ff c0 65 pfld.q -8\(%r14\),%f0 + 2e4: 05 00 00 64 pfld.q 0\(%r0\)\+\+,%f0 + 2e8: 85 00 24 64 pfld.q 128\(%r1\)\+\+,%f4 + 2ec: 05 01 48 64 pfld.q 256\(%sp\)\+\+,%f8 + 2f0: 05 02 6c 64 pfld.q 512\(%fp\)\+\+,%f12 + 2f4: 05 04 90 64 pfld.q 1024\(%r4\)\+\+,%f16 + 2f8: 05 10 b4 64 pfld.q 4096\(%r5\)\+\+,%f20 + 2fc: 05 20 d8 64 pfld.q 8192\(%r6\)\+\+,%f24 + 300: 05 40 fc 64 pfld.q 16384\(%r7\)\+\+,%f28 + 304: fd 7f e0 64 pfld.q 32760\(%r7\)\+\+,%f0 + 308: 05 80 e4 64 pfld.q -32768\(%r7\)\+\+,%f4 + 30c: 05 c0 08 65 pfld.q -16384\(%r8\)\+\+,%f8 + 310: 05 e0 2c 65 pfld.q -8192\(%r9\)\+\+,%f12 + 314: 05 f0 50 65 pfld.q -4096\(%r10\)\+\+,%f16 + 318: 05 fc 74 65 pfld.q -1024\(%r11\)\+\+,%f20 + 31c: 05 fe 98 65 pfld.q -512\(%r12\)\+\+,%f24 + 320: 0d ff bc 65 pfld.q -248\(%r13\)\+\+,%f28 + 324: fd ff d0 65 pfld.q -8\(%r14\)\+\+,%f16 + 328: 04 28 1c 60 pfld.q %r5\(%r0\),%f28 + 32c: 04 30 38 60 pfld.q %r6\(%r1\),%f24 + 330: 04 38 54 60 pfld.q %r7\(%sp\),%f20 + 334: 04 40 70 60 pfld.q %r8\(%fp\),%f16 + 338: 04 48 8c 60 pfld.q %r9\(%r4\),%f12 + 33c: 04 00 a8 60 pfld.q %r0\(%r5\),%f8 + 340: 04 08 c4 60 pfld.q %r1\(%r6\),%f4 + 344: 04 60 e0 60 pfld.q %r12\(%r7\),%f0 + 348: 04 68 1c 61 pfld.q %r13\(%r8\),%f28 + 34c: 04 70 38 61 pfld.q %r14\(%r9\),%f24 + 350: 04 78 54 61 pfld.q %r15\(%r10\),%f20 + 354: 04 80 70 61 pfld.q %r16\(%r11\),%f16 + 358: 04 88 8c 61 pfld.q %r17\(%r12\),%f12 + 35c: 04 e0 a8 61 pfld.q %r28\(%r13\),%f8 + 360: 04 f8 c4 61 pfld.q %r31\(%r14\),%f4 + 364: 05 28 00 60 pfld.q %r5\(%r0\)\+\+,%f0 + 368: 05 30 24 60 pfld.q %r6\(%r1\)\+\+,%f4 + 36c: 05 38 48 60 pfld.q %r7\(%sp\)\+\+,%f8 + 370: 05 40 6c 60 pfld.q %r8\(%fp\)\+\+,%f12 + 374: 05 48 90 60 pfld.q %r9\(%r4\)\+\+,%f16 + 378: 05 00 b4 60 pfld.q %r0\(%r5\)\+\+,%f20 + 37c: 05 08 d8 60 pfld.q %r1\(%r6\)\+\+,%f24 + 380: 05 60 fc 60 pfld.q %r12\(%r7\)\+\+,%f28 + 384: 05 68 00 61 pfld.q %r13\(%r8\)\+\+,%f0 + 388: 05 70 24 61 pfld.q %r14\(%r9\)\+\+,%f4 + 38c: 05 78 48 61 pfld.q %r15\(%r10\)\+\+,%f8 + 390: 05 80 6c 61 pfld.q %r16\(%r11\)\+\+,%f12 + 394: 05 88 90 61 pfld.q %r17\(%r12\)\+\+,%f16 + 398: 05 e0 b4 61 pfld.q %r28\(%r13\)\+\+,%f20 + 39c: 05 f8 d8 61 pfld.q %r31\(%r14\)\+\+,%f24 diff --git a/gas/testsuite/gas/i860/xp.s b/gas/testsuite/gas/i860/xp.s new file mode 100644 index 00000000000..406c8f0fe05 --- /dev/null +++ b/gas/testsuite/gas/i860/xp.s @@ -0,0 +1,266 @@ +# This tests the XP-only instructions: +# ldint.x, ldio.x, stio.x, scyc.b, pfld.q +# And control registers: +# %bear, %ccr, %p0, %p1, %p2, %p3 + + .text + + # XP-only control registers + ld.c %bear,%r31 + ld.c %bear,%r0 + ld.c %ccr,%r5 + ld.c %ccr,%r30 + ld.c %p0,%r10 + ld.c %p0,%r2 + ld.c %p1,%r21 + ld.c %p1,%r0 + ld.c %p2,%r28 + ld.c %p2,%r12 + ld.c %p3,%r31 + ld.c %p3,%r6 + + st.c %r0,%bear + st.c %r30,%bear + st.c %r7,%ccr + st.c %r31,%ccr + st.c %r11,%p0 + st.c %r3,%p0 + st.c %r22,%p1 + st.c %r15,%p1 + st.c %r29,%p2 + st.c %r13,%p2 + st.c %r4,%p3 + st.c %r6,%p3 + + # ldint.{s,b,l} + ldint.l %r0,%r5 + ldint.l %r6,%r31 + ldint.l %r7,%r30 + ldint.l %r8,%r29 + ldint.l %r9,%r28 + ldint.l %r0,%r27 + ldint.l %r1,%r26 + ldint.l %r12,%r25 + ldint.l %r13,%r24 + ldint.l %r14,%r23 + ldint.l %r15,%r22 + ldint.l %r16,%r21 + ldint.l %r17,%r20 + ldint.l %r28,%r19 + ldint.l %r31,%r18 + + ldint.s %r0,%r5 + ldint.s %r6,%r31 + ldint.s %r7,%r30 + ldint.s %r8,%r29 + ldint.s %r9,%r28 + ldint.s %r0,%r27 + ldint.s %r1,%r26 + ldint.s %r12,%r25 + ldint.s %r13,%r24 + ldint.s %r14,%r23 + ldint.s %r15,%r22 + ldint.s %r16,%r21 + ldint.s %r17,%r20 + ldint.s %r28,%r19 + ldint.s %r31,%r18 + + ldint.b %r0,%r5 + ldint.b %r6,%r31 + ldint.b %r7,%r30 + ldint.b %r8,%r29 + ldint.b %r9,%r28 + ldint.b %r0,%r27 + ldint.b %r1,%r26 + ldint.b %r12,%r25 + ldint.b %r13,%r24 + ldint.b %r14,%r23 + ldint.b %r15,%r22 + ldint.b %r16,%r21 + ldint.b %r17,%r20 + ldint.b %r28,%r19 + ldint.b %r31,%r18 + + # ldio.{s,b,l} + ldio.l %r0,%r5 + ldio.l %r6,%r31 + ldio.l %r7,%r30 + ldio.l %r8,%r29 + ldio.l %r9,%r28 + ldio.l %r0,%r27 + ldio.l %r1,%r26 + ldio.l %r12,%r25 + ldio.l %r13,%r24 + ldio.l %r14,%r23 + ldio.l %r15,%r22 + ldio.l %r16,%r21 + ldio.l %r17,%r20 + ldio.l %r28,%r19 + ldio.l %r31,%r18 + + ldio.s %r0,%r5 + ldio.s %r6,%r31 + ldio.s %r7,%r30 + ldio.s %r8,%r29 + ldio.s %r9,%r28 + ldio.s %r0,%r27 + ldio.s %r1,%r26 + ldio.s %r12,%r25 + ldio.s %r13,%r24 + ldio.s %r14,%r23 + ldio.s %r15,%r22 + ldio.s %r16,%r21 + ldio.s %r17,%r20 + ldio.s %r28,%r19 + ldio.s %r31,%r18 + + ldio.b %r0,%r5 + ldio.b %r6,%r31 + ldio.b %r7,%r30 + ldio.b %r8,%r29 + ldio.b %r9,%r28 + ldio.b %r0,%r27 + ldio.b %r1,%r26 + ldio.b %r12,%r25 + ldio.b %r13,%r24 + ldio.b %r14,%r23 + ldio.b %r15,%r22 + ldio.b %r16,%r21 + ldio.b %r17,%r20 + ldio.b %r28,%r19 + ldio.b %r31,%r18 + + # stio.{s,b,l} + stio.l %r0,%r5 + stio.l %r6,%r31 + stio.l %r7,%r30 + stio.l %r8,%r29 + stio.l %r9,%r28 + stio.l %r0,%r27 + stio.l %r1,%r26 + stio.l %r12,%r25 + stio.l %r13,%r24 + stio.l %r14,%r23 + stio.l %r15,%r22 + stio.l %r16,%r21 + stio.l %r17,%r20 + stio.l %r28,%r19 + stio.l %r31,%r18 + + stio.s %r0,%r5 + stio.s %r6,%r31 + stio.s %r7,%r30 + stio.s %r8,%r29 + stio.s %r9,%r28 + stio.s %r0,%r27 + stio.s %r1,%r26 + stio.s %r12,%r25 + stio.s %r13,%r24 + stio.s %r14,%r23 + stio.s %r15,%r22 + stio.s %r16,%r21 + stio.s %r17,%r20 + stio.s %r28,%r19 + stio.s %r31,%r18 + + stio.b %r0,%r5 + stio.b %r6,%r31 + stio.b %r7,%r30 + stio.b %r8,%r29 + stio.b %r9,%r28 + stio.b %r0,%r27 + stio.b %r1,%r26 + stio.b %r12,%r25 + stio.b %r13,%r24 + stio.b %r14,%r23 + stio.b %r15,%r22 + stio.b %r16,%r21 + stio.b %r17,%r20 + stio.b %r28,%r19 + stio.b %r31,%r18 + + # scyc.b + scyc.b %r0 + scyc.b %r5 + scyc.b %r6 + scyc.b %r13 + scyc.b %r14 + scyc.b %r28 + scyc.b %r29 + scyc.b %r30 + scyc.b %r31 + + # pfld.q + # Immediate form, no auto-increment. + pfld.q 0(%r0),%f0 + pfld.q 128(%r1),%f28 + pfld.q 256(%r2),%f24 + pfld.q 512(%r3),%f20 + pfld.q 1024(%r4),%f16 + pfld.q 4096(%r5),%f12 + pfld.q 8192(%r6),%f8 + pfld.q 16384(%r7),%f4 + pfld.q 32760(%r7),%f0 + pfld.q -32768(%r7),%f28 + pfld.q -16384(%r8),%f24 + pfld.q -8192(%r9),%f20 + pfld.q -4096(%r10),%f16 + pfld.q -1024(%r11),%f12 + pfld.q -512(%r12),%f8 + pfld.q -248(%r13),%f4 + pfld.q -8(%r14),%f0 + + # Immediate form, with auto-increment. + pfld.q 0(%r0)++,%f0 + pfld.q 128(%r1)++,%f4 + pfld.q 256(%r2)++,%f8 + pfld.q 512(%r3)++,%f12 + pfld.q 1024(%r4)++,%f16 + pfld.q 4096(%r5)++,%f20 + pfld.q 8192(%r6)++,%f24 + pfld.q 16384(%r7)++,%f28 + pfld.q 32760(%r7)++,%f0 + pfld.q -32768(%r7)++,%f4 + pfld.q -16384(%r8)++,%f8 + pfld.q -8192(%r9)++,%f12 + pfld.q -4096(%r10)++,%f16 + pfld.q -1024(%r11)++,%f20 + pfld.q -512(%r12)++,%f24 + pfld.q -248(%r13)++,%f28 + pfld.q -8(%r14)++,%f16 + + # Index form, no auto-increment. + pfld.q %r5(%r0),%f28 + pfld.q %r6(%r1),%f24 + pfld.q %r7(%r2),%f20 + pfld.q %r8(%r3),%f16 + pfld.q %r9(%r4),%f12 + pfld.q %r0(%r5),%f8 + pfld.q %r1(%r6),%f4 + pfld.q %r12(%r7),%f0 + pfld.q %r13(%r8),%f28 + pfld.q %r14(%r9),%f24 + pfld.q %r15(%r10),%f20 + pfld.q %r16(%r11),%f16 + pfld.q %r17(%r12),%f12 + pfld.q %r28(%r13),%f8 + pfld.q %r31(%r14),%f4 + + # Index form, with auto-increment. + pfld.q %r5(%r0)++,%f0 + pfld.q %r6(%r1)++,%f4 + pfld.q %r7(%r2)++,%f8 + pfld.q %r8(%r3)++,%f12 + pfld.q %r9(%r4)++,%f16 + pfld.q %r0(%r5)++,%f20 + pfld.q %r1(%r6)++,%f24 + pfld.q %r12(%r7)++,%f28 + pfld.q %r13(%r8)++,%f0 + pfld.q %r14(%r9)++,%f4 + pfld.q %r15(%r10)++,%f8 + pfld.q %r16(%r11)++,%f12 + pfld.q %r17(%r12)++,%f16 + pfld.q %r28(%r13)++,%f20 + pfld.q %r31(%r14)++,%f24 + + diff --git a/gdb/Makefile.in b/gdb/Makefile.in index 8cd12460000..a90c51b12b0 100644 --- a/gdb/Makefile.in +++ b/gdb/Makefile.in @@ -752,6 +752,7 @@ ALL_64_TARGET_OBS = \ arch/riscv.o \ bpf-tdep.o \ ia64-linux-tdep.o \ + i860-tdep.o \ ia64-tdep.o \ ia64-vms-tdep.o \ loongarch-linux-tdep.o \ diff --git a/gdb/configure.tgt b/gdb/configure.tgt index b9e0f80ce6a..d6af668e2fb 100644 --- a/gdb/configure.tgt +++ b/gdb/configure.tgt @@ -291,6 +291,11 @@ hppa*-*-openbsd*) gdb_target_obs="hppa-bsd-tdep.o hppa-obsd-tdep.o solib-svr4.o" ;; +i860-*-*) + # Target: Intel i860 + gdb_target_obs="i860-tdep.o" + ;; + i[34567]86-*-darwin*) # Target: Darwin/i386 gdb_target_obs="i386-darwin-tdep.o solib-darwin.o" diff --git a/gdb/i860-tdep.c b/gdb/i860-tdep.c new file mode 100644 index 00000000000..09b4aa9dd2f --- /dev/null +++ b/gdb/i860-tdep.c @@ -0,0 +1,477 @@ +/* Target-dependent code for the Intel i860. + Copyright (C) 2026 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe + + This file is part of GDB. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +#include "arch-utils.h" +#include "dwarf2/frame.h" +#include "extract-store-integer.h" +#include "frame-base.h" +#include "frame-unwind.h" +#include "gdbarch.h" +#include "gdbcore.h" +#include "gdbtypes.h" +#include "regcache.h" +#include "symtab.h" +#include "target.h" +#include "trad-frame.h" +#include "value.h" + +/* The order of user_regs_struct of the Linux port, DWARF numbers for r and f. */ +enum +{ + I860_R0_REGNUM = 0, + I860_R1_REGNUM = 1, + I860_SP_REGNUM = 2, + I860_FP_REGNUM = 3, + I860_R16_REGNUM = 16, + I860_F0_REGNUM = 32, + I860_F8_REGNUM = 40, + I860_PSR_REGNUM = 64, + I860_EPSR_REGNUM = 65, + I860_FIR_REGNUM = 66, + I860_FSR_REGNUM = 67, + I860_NUM_REGS = 68 +}; + +/* trap %r0,%r0,%r1: the Linux port raises SIGTRAP for it in a traced process. */ +constexpr gdb_byte i860_break_insn[] = { 0x00, 0x00, 0x01, 0x44 }; + +using i860_breakpoint = BP_MANIPULATION (i860_break_insn); + +static const char * +i860_register_name (struct gdbarch *gdbarch, int regnum) +{ + static const char *const names[I860_NUM_REGS] = + { + "r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", + "psr", "epsr", "fir", "fsr" + }; + + return names[regnum]; +} + +static struct type * +i860_register_type (struct gdbarch *gdbarch, int regnum) +{ + if (regnum == I860_FIR_REGNUM) + return builtin_type (gdbarch)->builtin_func_ptr; + if (regnum == I860_SP_REGNUM || regnum == I860_FP_REGNUM) + return builtin_type (gdbarch)->builtin_data_ptr; + if (regnum >= I860_F0_REGNUM && regnum < I860_PSR_REGNUM) + return builtin_type (gdbarch)->builtin_float; + if (regnum >= I860_PSR_REGNUM) + return builtin_type (gdbarch)->builtin_uint32; + return builtin_type (gdbarch)->builtin_int32; +} + +/* Fallback without unwind information: what the code of the prologue says. Functions can do + without a frame or a frame pointer, and then r3 holds anything. */ + +struct i860_prologue +{ + /* relative to the stack pointer at the entry */ + LONGEST sp_adjust = 0; + bool have_fp = false; + LONGEST fp_offset = 0; + /* -1: not saved */ + LONGEST saved[16]; + CORE_ADDR end = 0; + + i860_prologue () + { + for (LONGEST &r : saved) + r = -1; + } +}; + +/* The addr of an instruction that ends a prologue at the latest */ +static bool +i860_insn_is_control (uint32_t insn) +{ + switch (insn >> 26) + { + case 0x10: /* bri */ + case 0x13: /* calli, core escape */ + case 0x14: case 0x15: case 0x16: case 0x17: /* bte, btne */ + case 0x1a: case 0x1b: /* br, call */ + case 0x1c: case 0x1d: case 0x1e: case 0x1f: /* bc, bc.t, bnc, bnc.t */ + case 0x2d: /* bla */ + return true; + default: + return false; + } +} + +/* Through the code cache: over a serial line a word at a time is slow. */ +static bool +i860_read_insn (CORE_ADDR addr, uint32_t *insn) +{ + gdb_byte buf[4]; + + if (target_read_code (addr, buf, sizeof (buf)) != 0) + return false; + *insn = extract_unsigned_integer (buf, sizeof (buf), BFD_ENDIAN_LITTLE); + return true; +} + +/* Look at what ran between FUNC and PC. */ +static void +i860_analyze_prologue (CORE_ADDR func, CORE_ADDR pc, struct i860_prologue *p) +{ + uint32_t r31 = 0; + CORE_ADDR limit = std::min (pc, func + 64 * 4); + + p->end = func; + for (CORE_ADDR a = func; a < limit; a += 4) + { + uint32_t insn; + + if (!i860_read_insn (a, &insn)) + break; + + unsigned int src1 = (insn >> 11) & 31, src2 = (insn >> 21) & 31; + unsigned int dest = (insn >> 16) & 31; + LONGEST imm = (int16_t) insn; + + if (i860_insn_is_control (insn)) + break; + + if ((insn >> 26) == 0x21 && src2 == I860_SP_REGNUM && dest == I860_SP_REGNUM) + p->sp_adjust += imm; + else if ((insn >> 26) == 0x21 && src2 == I860_SP_REGNUM && dest == I860_FP_REGNUM) + { + p->have_fp = true; + p->fp_offset = p->sp_adjust + imm; + } + else if ((insn & 0xfc000000) == 0xa0000000 && src1 == 0 + && src2 == I860_SP_REGNUM && dest == I860_FP_REGNUM) + { + p->have_fp = true; + p->fp_offset = p->sp_adjust; + } + else if ((insn & 0xfc000000) == 0x80000000 && src1 == 31 + && src2 == I860_SP_REGNUM && dest == I860_SP_REGNUM) + p->sp_adjust += (int32_t) r31; + else if ((insn >> 26) == 0x3b && src2 == 0 && dest == 31) + r31 = insn << 16; + else if ((insn >> 26) == 0x39 && src2 == 31 && dest == 31) + r31 |= insn & 0xffff; + else if ((insn & 0xfc000001) == 0x1c000001 + && (src2 == I860_SP_REGNUM || src2 == I860_FP_REGNUM)) + { + /* st.l, the displacement in two parts and bit 0 being the size */ + LONGEST disp = (int16_t) (((insn >> 5) & 0xf800) | (insn & 0x7fe)); + LONGEST off = disp + (src2 == I860_SP_REGNUM ? p->sp_adjust : p->fp_offset); + + if (src2 == I860_FP_REGNUM && !p->have_fp) + continue; + if (src1 < 16 && src1 != 0 && p->saved[src1] == -1) + p->saved[src1] = off; + } + else + { + /* the prologue is what comes before the first other instruction, moves of + arguments to registers aside */ + if (p->sp_adjust != 0 && p->end == func) + p->end = a; + continue; + } + p->end = a + 4; + } +} + +static CORE_ADDR +i860_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) +{ + CORE_ADDR func; + + if (find_pc_partial_function (pc, nullptr, &func, nullptr)) + { + CORE_ADDR end = skip_prologue_using_sal (gdbarch, func); + + if (end != 0) + return std::max (pc, end); + + struct i860_prologue p; + i860_analyze_prologue (func, func + 64 * 4, &p); + return std::max (pc, p.end); + } + return pc; +} + +static CORE_ADDR +i860_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) +{ + return sp & ~(CORE_ADDR) 15; +} + +/* No hardware single step: where can the instruction at the PC go? A breakpoint + cannot sit in a delay slot, so a delayed branch stops after it has run. */ +static std::vector +i860_software_single_step (struct regcache *regcache) +{ + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian order = gdbarch_byte_order_for_code (gdbarch); + CORE_ADDR pc = regcache_read_pc (regcache); + ULONGEST insn = read_memory_unsigned_integer (pc, 4, order); + unsigned int op = insn >> 26; + CORE_ADDR lbr = pc + 4 + (sign_extend (insn & 0x3ffffff, 26) << 2); + CORE_ADDR sbr = pc + 4 + (sign_extend (((insn >> 5) & 0xf800) | (insn & 0x7ff), 16) << 2); + ULONGEST src1; + + switch (op) + { + case 0x1a: /* br */ + case 0x1b: /* call */ + return { lbr }; + case 0x1c: /* bc */ + case 0x1e: /* bnc */ + return { pc + 4, lbr }; + case 0x1d: /* bc.t: the slot only runs if taken */ + case 0x1f: /* bnc.t */ + return { pc + 8, lbr }; + case 0x14: case 0x15: /* btne */ + case 0x16: case 0x17: /* bte */ + return { pc + 4, sbr }; + case 0x2d: /* bla */ + return { pc + 8, sbr }; + case 0x10: /* bri */ + regcache->raw_read ((insn >> 11) & 31, &src1); + return { src1 & ~(CORE_ADDR) 3 }; + case 0x13: /* core escape */ + if ((insn & 7) == 2) /* calli */ + { + regcache->raw_read ((insn >> 11) & 31, &src1); + return { src1 & ~(CORE_ADDR) 3 }; + } + break; + } + return { pc + 4 }; +} + +/* Integers in r16 and r17, floating point in f8 and f9, aggregates in memory. */ +static enum return_value_convention +i860_return_value (struct gdbarch *gdbarch, struct value *function, + struct type *type, struct regcache *regcache, + gdb_byte *readbuf, const gdb_byte *writebuf) +{ + int len = type->length (); + int regnum; + + if (type->code () == TYPE_CODE_STRUCT || type->code () == TYPE_CODE_UNION + || type->code () == TYPE_CODE_ARRAY || len > 8) + { + if (readbuf != nullptr) + { + ULONGEST addr; + + regcache->cooked_read (I860_R16_REGNUM, &addr); + read_memory (addr, readbuf, len); + } + return RETURN_VALUE_ABI_RETURNS_ADDRESS; + } + + regnum = type->code () == TYPE_CODE_FLT ? I860_F8_REGNUM : I860_R16_REGNUM; + for (int i = 0; i < len; i += 4, regnum++) + { + gdb_byte buf[4]; + + if (readbuf != nullptr) + { + regcache->cooked_read (regnum, buf); + memcpy (readbuf + i, buf, std::min (len - i, 4)); + } + if (writebuf != nullptr) + { + memset (buf, 0, 4); + memcpy (buf, writebuf + i, std::min (len - i, 4)); + regcache->cooked_write (regnum, buf); + } + } + return RETURN_VALUE_REGISTER_CONVENTION; +} + +static void +i860_dwarf2_init_reg (struct gdbarch *gdbarch, int regnum, + struct dwarf2_frame_state_reg *reg, + const frame_info_ptr &this_frame) +{ + if (regnum == I860_FIR_REGNUM) + reg->how = DWARF2_FRAME_REG_RA; + else if (regnum == I860_SP_REGNUM) + reg->how = DWARF2_FRAME_REG_CFA; +} + +/* Without a symbol: at the allocation of its frame, or after the last return before it, whose + delay slot follows it. An early return in a function with a frame misleads this. */ +static CORE_ADDR +i860_find_function_start (CORE_ADDR pc) +{ + for (CORE_ADDR a = pc & ~(CORE_ADDR) 3; a >= 8 && pc - a < 0x10000; a -= 4) + { + uint32_t insn; + + /* addu -N,%sp,%sp */ + if (i860_read_insn (a, &insn) && (insn & 0xffff8000) == 0x84428000) + return a; + if (!i860_read_insn (a - 8, &insn)) + return a; + /* bri, or br */ + if ((insn & 0xffff07ff) == 0x40000000 || (insn >> 26) == 0x1a) + return a; + } + return pc; +} + +/* The function of THIS_FRAME, what has run of its prologue in P. */ +static CORE_ADDR +i860_frame_prologue (const frame_info_ptr &this_frame, struct i860_prologue *p) +{ + CORE_ADDR pc = get_frame_pc (this_frame), func = get_frame_func (this_frame); + + if (func == 0) + func = i860_find_function_start (pc); + i860_analyze_prologue (func, pc, p); + return func; +} + +static struct trad_frame_cache * +i860_frame_cache (const frame_info_ptr &this_frame, void **cache) +{ + struct trad_frame_cache *info; + struct i860_prologue p; + CORE_ADDR pc, func, cfa; + + if (*cache != nullptr) + return (struct trad_frame_cache *) *cache; + + info = trad_frame_cache_zalloc (this_frame); + *cache = info; + + pc = get_frame_pc (this_frame); + func = i860_frame_prologue (this_frame, &p); + + if (p.have_fp) + cfa = get_frame_register_unsigned (this_frame, I860_FP_REGNUM) - p.fp_offset; + else + cfa = get_frame_register_unsigned (this_frame, I860_SP_REGNUM) - p.sp_adjust; + + trad_frame_set_id (info, frame_id_build (cfa, func)); + trad_frame_set_reg_value (info, I860_SP_REGNUM, cfa); + for (int r = 1; r < 16; r++) + if (p.saved[r] != -1) + trad_frame_set_reg_addr (info, r, cfa + p.saved[r]); + if (p.saved[I860_R1_REGNUM] != -1) + trad_frame_set_reg_addr (info, I860_FIR_REGNUM, cfa + p.saved[I860_R1_REGNUM]); + else + trad_frame_set_reg_value (info, I860_FIR_REGNUM, + get_frame_register_unsigned (this_frame, I860_R1_REGNUM)); + return info; +} + +static enum unwind_stop_reason +i860_frame_stop_reason (const frame_info_ptr &this_frame, void **cache) +{ + struct trad_frame_cache *info = i860_frame_cache (this_frame, cache); + + CORE_ADDR ra = value_as_long (trad_frame_get_register (info, this_frame, I860_FIR_REGNUM)); + struct i860_prologue p; + + /* the process entry has no return address: r1 is zero or from its own call */ + i860_frame_prologue (this_frame, &p); + if (ra == 0 || (ra == get_frame_pc (this_frame) && p.saved[I860_R1_REGNUM] == -1)) + return UNWIND_OUTERMOST; + return default_frame_unwind_stop_reason (this_frame, cache); +} + +static void +i860_frame_this_id (const frame_info_ptr &this_frame, void **cache, + struct frame_id *this_id) +{ + trad_frame_get_id (i860_frame_cache (this_frame, cache), this_id); +} + +static struct value * +i860_frame_prev_register (const frame_info_ptr &this_frame, void **cache, + int regnum) +{ + return trad_frame_get_register (i860_frame_cache (this_frame, cache), + this_frame, regnum); +} + +static const struct frame_unwind_legacy i860_frame_unwind ( + "i860 prologue", + NORMAL_FRAME, + FRAME_UNWIND_ARCH, + i860_frame_stop_reason, + i860_frame_this_id, + i860_frame_prev_register, + nullptr, + default_frame_sniffer +); + +static struct gdbarch * +i860_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +{ + struct gdbarch *gdbarch; + + arches = gdbarch_list_lookup_by_info (arches, &info); + if (arches != nullptr) + return arches->gdbarch; + + gdbarch = gdbarch_alloc (&info, nullptr); + + set_gdbarch_long_double_bit (gdbarch, 64); + set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); + + set_gdbarch_num_regs (gdbarch, I860_NUM_REGS); + set_gdbarch_sp_regnum (gdbarch, I860_SP_REGNUM); + set_gdbarch_pc_regnum (gdbarch, I860_FIR_REGNUM); + set_gdbarch_ps_regnum (gdbarch, I860_PSR_REGNUM); + set_gdbarch_fp0_regnum (gdbarch, I860_F0_REGNUM); + set_gdbarch_register_name (gdbarch, i860_register_name); + set_gdbarch_register_type (gdbarch, i860_register_type); + + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + set_gdbarch_frame_align (gdbarch, i860_frame_align); + set_gdbarch_skip_prologue (gdbarch, i860_skip_prologue); + set_gdbarch_return_value (gdbarch, i860_return_value); + set_gdbarch_breakpoint_kind_from_pc (gdbarch, i860_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, i860_breakpoint::bp_from_kind); + set_gdbarch_get_next_pcs (gdbarch, i860_software_single_step); + /* the data breakpoint traps before the access */ + set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); + + dwarf2_frame_set_init_reg (gdbarch, i860_dwarf2_init_reg); + dwarf2_append_unwinders (gdbarch); + frame_unwind_append_unwinder (gdbarch, &i860_frame_unwind); + + return gdbarch; +} + +INIT_GDB_FILE (i860_tdep) +{ + gdbarch_register (bfd_arch_i860, i860_gdbarch_init); +} diff --git a/include/elf/i860.h b/include/elf/i860.h index 45a7225b4be..cc033a6ebf9 100644 --- a/include/elf/i860.h +++ b/include/elf/i860.h @@ -33,6 +33,17 @@ START_RELOC_NUMBERS (elf_i860_reloc_type) RELOC_NUMBER (R_860_GLOB_DAT, 0x03) /* S, Create GOT entry */ RELOC_NUMBER (R_860_JUMP_SLOT, 0x04) /* S+A, Create PLT entry */ RELOC_NUMBER (R_860_RELATIVE, 0x05) /* B+A, Adj by program base */ + RELOC_NUMBER (R_860_TLS_DTPMOD32, 0x06) /* module of the symbol */ + RELOC_NUMBER (R_860_TLS_DTPOFF32, 0x07) /* offset in its TLS block */ + RELOC_NUMBER (R_860_TLS_TPOFF32, 0x08) /* offset from the thread pointer */ + RELOC_NUMBER (R_860_TLS_GD_HI, 0x10) /* GOT offset of a DTPMOD, DTPOFF pair >> 16 */ + RELOC_NUMBER (R_860_TLS_GD_LO, 0x11) + RELOC_NUMBER (R_860_TLS_IE_HA, 0x12) /* hiadj(GOT offset of a TPOFF) */ + RELOC_NUMBER (R_860_TLS_IE_LO1, 0x13) + RELOC_NUMBER (R_860_TLS_IE_ABS_HA, 0x14) /* hiadj(address of a TPOFF) */ + RELOC_NUMBER (R_860_TLS_IE_ABS_LO1, 0x15) + RELOC_NUMBER (R_860_TLS_LE_HI, 0x16) /* offset from the thread pointer >> 16 */ + RELOC_NUMBER (R_860_TLS_LE_LO, 0x17) RELOC_NUMBER (R_860_PC26, 0x30) /* (S+A-P) >> 2 */ RELOC_NUMBER (R_860_PLT26, 0x31) /* (L+A-P) >> 2 */ RELOC_NUMBER (R_860_PC16, 0x32) /* (S+A-P) >> 2 */ diff --git a/include/opcode/i860.h b/include/opcode/i860.h new file mode 100644 index 00000000000..717a9dd3111 --- /dev/null +++ b/include/opcode/i860.h @@ -0,0 +1,507 @@ +/* Table of opcodes for the i860. + Copyright (C) 1989-2018 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe + + This file is part of the GNU opcodes library. + + GAS/GDB is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS/GDB is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS or GDB; see the file COPYING3. If not, write to + the Free Software Foundation, 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +/* Structure of an opcode table entry. */ +struct i860_opcode +{ + /* The opcode name. */ + const char *name; + + /* Bits that must be set. */ + unsigned long match; + + /* Bits that must not be set. */ + unsigned long lose; + + const char *args; + + /* Nonzero if this is a possible expand-instruction. */ + char expand; +}; + + +enum expand_type +{ + E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY +}; + + +/* All i860 opcodes are 32 bits, except for the pseudo-instructions + and the operations utilizing a 32-bit address expression, an + unsigned 32-bit constant, or a signed 32-bit constant. + These opcodes are expanded into a two-instruction sequence for + any situation where the immediate operand does not fit in 32 bits. + In the case of the add and subtract operations the expansion is + to a three-instruction sequence (ex: orh, or, adds). In cases + where the address is to be relocated, the instruction is + expanded to handle the worse case, this could be optimized at + the final link if the actual address were known. + + The pseudoinstructions are: mov, fmov, pmov, nop, and fnop. + These instructions are implemented as a one or two instruction + sequence of other operations. + + The match component is a mask saying which bits must match a + particular opcode in order for an instruction to be an instance + of that opcode. + + The args component is a string containing one character + for each operand of the instruction. + +Kinds of operands: + # Number used by optimizer. It is ignored. + 1 src1 integer register. + 2 src2 integer register. + d dest register. + c ctrlreg control register. + i 16 bit immediate. + I 16 bit immediate, aligned 2^0. (ld.b) + J 16 bit immediate, aligned 2^1. (ld.s) + K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l) + L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d) + M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q) + 5 5 bit immediate. + l lbroff 26 bit PC relative immediate. + r sbroff 16 bit PC relative immediate. + s split 16 bit immediate. + S split 16 bit immediate, aligned 2^0. (st.b) + T split 16 bit immediate, aligned 2^1. (st.s) + U split 16 bit immediate, aligned 2^2. (st.l) + e src1 floating point register. + f src2 floating point register. + g dest floating point register. */ + + +/* The order of the opcodes in this table is significant. The assembler + requires that all instances of the same mnemonic must be consecutive. + If they aren't, the assembler will not function properly. + + The order of opcodes does not affect the disassembler. */ + +static const struct i860_opcode i860_opcodes[] = +{ +/* REG-Format Instructions. */ +{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ +{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ +{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ +{ "ld.s", 0x10000000, 0xec000001, "1(2),d", 0 }, /* ld.s isrc1(isrc2),idest */ +{ "ld.s", 0x14000000, 0xe8000001, "J(2),d", E_ADDR }, /* ld.s #const(isrc2),idest */ +{ "ld.l", 0x10000001, 0xec000000, "1(2),d", 0 }, /* ld.l isrc1(isrc2),idest */ +{ "ld.l", 0x14000001, 0xe8000000, "K(2),d", E_ADDR }, /* ld.l #const(isrc2),idest */ + +{ "st.c", 0x38000000, 0xc4000000, "1,c", 0 }, /* st.c isrc1ni,csrc2 */ +{ "st.b", 0x0c000000, 0xf0000000, "1,S(2)", E_ADDR }, /* st.b isrc1ni,#const(isrc2) */ +{ "st.s", 0x1c000000, 0xe0000001, "1,T(2)", E_ADDR }, /* st.s isrc1ni,#const(isrc2) */ +{ "st.l", 0x1c000001, 0xe0000000, "1,U(2)", E_ADDR }, /* st.l isrc1ni,#const(isrc2) */ + +{ "ixfr", 0x08000000, 0xf4000000, "1,g", 0 }, /* ixfr isrc1ni,fdest */ + +{ "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */ +{ "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */ +{ "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */ +{ "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */ +{ "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */ +{ "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */ +{ "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */ +{ "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */ +{ "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */ +{ "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */ +{ "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */ +{ "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */ + +{ "pfld.l", 0x60000002, 0x9c000001, "1(2),g", 0 }, /* pfld.l isrc1(isrc2),fdest */ +{ "pfld.l", 0x64000002, 0x98000001, "K(2),g", E_ADDR }, /* pfld.l #const(isrc2),fdest */ +{ "pfld.l", 0x60000003, 0x9c000000, "1(2)++,g", 0 }, /* pfld.l isrc1(isrc2)++,fdest */ +{ "pfld.l", 0x64000003, 0x98000000, "K(2)++,g", E_ADDR }, /* pfld.l #const(isrc2)++,fdest */ +{ "pfld.d", 0x60000000, 0x9c000007, "1(2),g", 0 }, /* pfld.d isrc1(isrc2),fdest */ +{ "pfld.d", 0x64000000, 0x98000007, "L(2),g", E_ADDR }, /* pfld.d #const(isrc2),fdest */ +{ "pfld.d", 0x60000001, 0x9c000006, "1(2)++,g", 0 }, /* pfld.d isrc1(isrc2)++,fdest */ +{ "pfld.d", 0x64000001, 0x98000006, "L(2)++,g", E_ADDR }, /* pfld.d #const(isrc2)++,fdest */ +{ "pfld.q", 0x60000004, 0x9c000003, "1(2),g", XP_ONLY }, /* pfld.q isrc1(isrc2),fdest */ +{ "pfld.q", 0x64000004, 0x98000003, "L(2),g", XP_ONLY }, /* pfld.q #const(isrc2),fdest */ +{ "pfld.q", 0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY }, /* pfld.q isrc1(isrc2)++,fdest */ +{ "pfld.q", 0x64000005, 0x98000002, "L(2)++,g", XP_ONLY }, /* pfld.q #const(isrc2)++,fdest */ + +{ "fst.l", 0x28000002, 0xd4000001, "g,1(2)", 0 }, /* fst.l fdest,isrc1(isrc2) */ +{ "fst.l", 0x2c000002, 0xd0000001, "g,K(2)", E_ADDR }, /* fst.l fdest,#const(isrc2) */ +{ "fst.l", 0x28000003, 0xd4000000, "g,1(2)++", 0 }, /* fst.l fdest,isrc1(isrc2)++ */ +{ "fst.l", 0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR }, /* fst.l fdest,#const(isrc2)++ */ +{ "fst.d", 0x28000000, 0xd4000007, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.d", 0x2c000000, 0xd0000007, "g,L(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.d", 0x28000001, 0xd4000006, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.d", 0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ +{ "fst.q", 0x28000004, 0xd4000003, "g,1(2)", 0 }, /* fst.d fdest,isrc1(isrc2) */ +{ "fst.q", 0x2c000004, 0xd0000003, "g,M(2)", E_ADDR }, /* fst.d fdest,#const(isrc2) */ +{ "fst.q", 0x28000005, 0xd4000002, "g,1(2)++", 0 }, /* fst.d fdest,isrc1(isrc2)++ */ +{ "fst.q", 0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR }, /* fst.d fdest,#const(isrc2)++ */ + +{ "pst.d", 0x3c000000, 0xc0000007, "g,L(2)", E_ADDR }, /* pst.d fdest,#const(isrc2) */ +{ "pst.d", 0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR }, /* pst.d fdest,#const(isrc2)++ */ + +{ "addu", 0x80000000, 0x7c000000, "1,2,d", 0 }, /* addu isrc1,isrc2,idest */ +{ "addu", 0x84000000, 0x78000000, "i,2,d", E_S32 }, /* addu #const,isrc2,idest */ +{ "adds", 0x90000000, 0x6c000000, "1,2,d", 0 }, /* adds isrc1,isrc2,idest */ +{ "adds", 0x94000000, 0x68000000, "i,2,d", E_S32 }, /* adds #const,isrc2,idest */ +{ "subu", 0x88000000, 0x74000000, "1,2,d", 0 }, /* subu isrc1,isrc2,idest */ +{ "subu", 0x8c000000, 0x70000000, "i,2,d", E_S32 }, /* subu #const,isrc2,idest */ +{ "subs", 0x98000000, 0x64000000, "1,2,d", 0 }, /* subs isrc1,isrc2,idest */ +{ "subs", 0x9c000000, 0x60000000, "i,2,d", E_S32 }, /* subs #const,isrc2,idest */ + +{ "shl", 0xa0000000, 0x5c000000, "1,2,d", 0 }, /* shl isrc1,isrc2,idest */ +{ "shl", 0xa4000000, 0x58000000, "i,2,d", 0 }, /* shl #const,isrc2,idest */ +{ "shr", 0xa8000000, 0x54000000, "1,2,d", 0 }, /* shr isrc1,isrc2,idest */ +{ "shr", 0xac000000, 0x50000000, "i,2,d", 0 }, /* shr #const,isrc2,idest */ +{ "shrd", 0xb0000000, 0x4c000000, "1,2,d", 0 }, /* shrd isrc1,isrc2,idest */ +{ "shra", 0xb8000000, 0x44000000, "1,2,d", 0 }, /* shra isrc1,isrc2,idest */ +{ "shra", 0xbc000000, 0x40000000, "i,2,d", 0 }, /* shra #const,isrc2,idest */ + +{ "mov", 0xa0000000, 0x5c00f800, "2,d", 0 }, /* shl r0,isrc2,idest */ +{ "mov", 0x94000000, 0x69e00000, "i,d", E_MOV }, /* adds #const,r0,idest */ +{ "nop", 0xa0000000, 0x5ffff800, "", 0 }, /* shl r0,r0,r0 */ +{ "fnop", 0xb0000000, 0x4ffff800, "", 0 }, /* shrd r0,r0,r0 */ + +{ "trap", 0x44000000, 0xb8000000, "1,2,d", 0 }, /* trap isrc1ni,isrc2,idest */ + +{ "flush", 0x34000004, 0xc81f0003, "L(2)", E_ADDR }, /* flush #const(isrc2) */ +{ "flush", 0x34000005, 0xc81f0002, "L(2)++", E_ADDR }, /* flush #const(isrc2)++ */ + +{ "and", 0xc0000000, 0x3c000000, "1,2,d", 0 }, /* and isrc1,isrc2,idest */ +{ "and", 0xc4000000, 0x38000000, "i,2,d", E_AND }, /* and #const,isrc2,idest */ +{ "andh", 0xcc000000, 0x30000000, "i,2,d", 0 }, /* andh #const,isrc2,idest */ +{ "andnot", 0xd0000000, 0x2c000000, "1,2,d", 0 }, /* andnot isrc1,isrc2,idest */ +{ "andnot", 0xd4000000, 0x28000000, "i,2,d", E_U32 }, /* andnot #const,isrc2,idest */ +{ "andnoth", 0xdc000000, 0x20000000, "i,2,d", 0 }, /* andnoth #const,isrc2,idest */ +{ "or", 0xe0000000, 0x1c000000, "1,2,d", 0 }, /* or isrc1,isrc2,idest */ +{ "or", 0xe4000000, 0x18000000, "i,2,d", E_U32 }, /* or #const,isrc2,idest */ +{ "orh", 0xec000000, 0x10000000, "i,2,d", 0 }, /* orh #const,isrc2,idest */ +{ "xor", 0xf0000000, 0x0c000000, "1,2,d", 0 }, /* xor isrc1,isrc2,idest */ +{ "xor", 0xf4000000, 0x08000000, "i,2,d", E_U32 }, /* xor #const,isrc2,idest */ +{ "xorh", 0xfc000000, 0x00000000, "i,2,d", 0 }, /* xorh #const,isrc2,idest */ + +{ "bte", 0x58000000, 0xa4000000, "1,2,r", 0 }, /* bte isrc1s,isrc2,sbroff */ +{ "bte", 0x5c000000, 0xa0000000, "5,2,r", 0 }, /* bte #const5,isrc2,sbroff */ +{ "btne", 0x50000000, 0xac000000, "1,2,r", 0 }, /* btne isrc1s,isrc2,sbroff */ +{ "btne", 0x54000000, 0xa8000000, "5,2,r", 0 }, /* btne #const5,isrc2,sbroff */ +{ "bla", 0xb4000000, 0x48000000, "1,2,r", E_DELAY }, /* bla isrc1s,isrc2,sbroff */ +{ "bri", 0x40000000, 0xbc000000, "1", E_DELAY }, /* bri isrc1ni */ + +/* Core Escape Instruction Format */ +{ "lock", 0x4c000001, 0xb000001e, "", 0 }, /* lock set BL in dirbase */ +{ "calli", 0x4c000002, 0xb000001d, "1", E_DELAY }, /* calli isrc1ni */ +{ "intovr", 0x4c000004, 0xb000001b, "", 0 }, /* intovr trap on integer overflow */ +{ "unlock", 0x4c000007, 0xb0000018, "", 0 }, /* unlock clear BL in dirbase */ +{ "ldio.l", 0x4c000408, 0xb00003f7, "2,d", XP_ONLY }, /* ldio.l isrc2,idest */ +{ "ldio.s", 0x4c000208, 0xb00005f7, "2,d", XP_ONLY }, /* ldio.s isrc2,idest */ +{ "ldio.b", 0x4c000008, 0xb00007f7, "2,d", XP_ONLY }, /* ldio.b isrc2,idest */ +{ "stio.l", 0x4c000409, 0xb00003f6, "1,2", XP_ONLY }, /* stio.l isrc1ni,isrc2 */ +{ "stio.s", 0x4c000209, 0xb00005f6, "1,2", XP_ONLY }, /* stio.s isrc1ni,isrc2 */ +{ "stio.b", 0x4c000009, 0xb00007f6, "1,2", XP_ONLY }, /* stio.b isrc1ni,isrc2 */ +{ "ldint.l", 0x4c00040a, 0xb00003f5, "2,d", XP_ONLY }, /* ldint.l isrc2,idest */ +{ "ldint.s", 0x4c00020a, 0xb00005f5, "2,d", XP_ONLY }, /* ldint.s isrc2,idest */ +{ "ldint.b", 0x4c00000a, 0xb00007f5, "2,d", XP_ONLY }, /* ldint.b isrc2,idest */ +{ "scyc.b", 0x4c00000b, 0xb00007f4, "2", XP_ONLY }, /* scyc.b isrc2 */ + +/* CTRL-Format Instructions */ +{ "br", 0x68000000, 0x94000000, "l", E_DELAY }, /* br lbroff */ +{ "call", 0x6c000000, 0x90000000, "l", E_DELAY }, /* call lbroff */ +{ "bc", 0x70000000, 0x8c000000, "l", 0 }, /* bc lbroff */ +{ "bc.t", 0x74000000, 0x88000000, "l", E_DELAY }, /* bc.t lbroff */ +{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ +{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ + +/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */ +{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, +{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, +{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, +{ "r2pt.ss", 0x48000401, 0xb40001fe, "e,f,g", 0 }, +{ "r2pt.sd", 0x48000481, 0xb400017e, "e,f,g", 0 }, +{ "r2pt.dd", 0x48000581, 0xb400007e, "e,f,g", 0 }, +{ "r2ap1.ss", 0x48000402, 0xb40001fd, "e,f,g", 0 }, +{ "r2ap1.sd", 0x48000482, 0xb400017d, "e,f,g", 0 }, +{ "r2ap1.dd", 0x48000582, 0xb400007d, "e,f,g", 0 }, +{ "r2apt.ss", 0x48000403, 0xb40001fc, "e,f,g", 0 }, +{ "r2apt.sd", 0x48000483, 0xb400017c, "e,f,g", 0 }, +{ "r2apt.dd", 0x48000583, 0xb400007c, "e,f,g", 0 }, +{ "i2p1.ss", 0x48000404, 0xb40001fb, "e,f,g", 0 }, +{ "i2p1.sd", 0x48000484, 0xb400017b, "e,f,g", 0 }, +{ "i2p1.dd", 0x48000584, 0xb400007b, "e,f,g", 0 }, +{ "i2pt.ss", 0x48000405, 0xb40001fa, "e,f,g", 0 }, +{ "i2pt.sd", 0x48000485, 0xb400017a, "e,f,g", 0 }, +{ "i2pt.dd", 0x48000585, 0xb400007a, "e,f,g", 0 }, +{ "i2ap1.ss", 0x48000406, 0xb40001f9, "e,f,g", 0 }, +{ "i2ap1.sd", 0x48000486, 0xb4000179, "e,f,g", 0 }, +{ "i2ap1.dd", 0x48000586, 0xb4000079, "e,f,g", 0 }, +{ "i2apt.ss", 0x48000407, 0xb40001f8, "e,f,g", 0 }, +{ "i2apt.sd", 0x48000487, 0xb4000178, "e,f,g", 0 }, +{ "i2apt.dd", 0x48000587, 0xb4000078, "e,f,g", 0 }, +{ "rat1p2.ss", 0x48000408, 0xb40001f7, "e,f,g", 0 }, +{ "rat1p2.sd", 0x48000488, 0xb4000177, "e,f,g", 0 }, +{ "rat1p2.dd", 0x48000588, 0xb4000077, "e,f,g", 0 }, +{ "m12apm.ss", 0x48000409, 0xb40001f6, "e,f,g", 0 }, +{ "m12apm.sd", 0x48000489, 0xb4000176, "e,f,g", 0 }, +{ "m12apm.dd", 0x48000589, 0xb4000076, "e,f,g", 0 }, +{ "ra1p2.ss", 0x4800040a, 0xb40001f5, "e,f,g", 0 }, +{ "ra1p2.sd", 0x4800048a, 0xb4000175, "e,f,g", 0 }, +{ "ra1p2.dd", 0x4800058a, 0xb4000075, "e,f,g", 0 }, +{ "m12ttpa.ss", 0x4800040b, 0xb40001f4, "e,f,g", 0 }, +{ "m12ttpa.sd", 0x4800048b, 0xb4000174, "e,f,g", 0 }, +{ "m12ttpa.dd", 0x4800058b, 0xb4000074, "e,f,g", 0 }, +{ "iat1p2.ss", 0x4800040c, 0xb40001f3, "e,f,g", 0 }, +{ "iat1p2.sd", 0x4800048c, 0xb4000173, "e,f,g", 0 }, +{ "iat1p2.dd", 0x4800058c, 0xb4000073, "e,f,g", 0 }, +{ "m12tpm.ss", 0x4800040d, 0xb40001f2, "e,f,g", 0 }, +{ "m12tpm.sd", 0x4800048d, 0xb4000172, "e,f,g", 0 }, +{ "m12tpm.dd", 0x4800058d, 0xb4000072, "e,f,g", 0 }, +{ "ia1p2.ss", 0x4800040e, 0xb40001f1, "e,f,g", 0 }, +{ "ia1p2.sd", 0x4800048e, 0xb4000171, "e,f,g", 0 }, +{ "ia1p2.dd", 0x4800058e, 0xb4000071, "e,f,g", 0 }, +{ "m12tpa.ss", 0x4800040f, 0xb40001f0, "e,f,g", 0 }, +{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, +{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */ +{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, +{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, +{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, +{ "r2st.ss", 0x48000411, 0xb40001ee, "e,f,g", 0 }, +{ "r2st.sd", 0x48000491, 0xb400016e, "e,f,g", 0 }, +{ "r2st.dd", 0x48000591, 0xb400006e, "e,f,g", 0 }, +{ "r2as1.ss", 0x48000412, 0xb40001ed, "e,f,g", 0 }, +{ "r2as1.sd", 0x48000492, 0xb400016d, "e,f,g", 0 }, +{ "r2as1.dd", 0x48000592, 0xb400006d, "e,f,g", 0 }, +{ "r2ast.ss", 0x48000413, 0xb40001ec, "e,f,g", 0 }, +{ "r2ast.sd", 0x48000493, 0xb400016c, "e,f,g", 0 }, +{ "r2ast.dd", 0x48000593, 0xb400006c, "e,f,g", 0 }, +{ "i2s1.ss", 0x48000414, 0xb40001eb, "e,f,g", 0 }, +{ "i2s1.sd", 0x48000494, 0xb400016b, "e,f,g", 0 }, +{ "i2s1.dd", 0x48000594, 0xb400006b, "e,f,g", 0 }, +{ "i2st.ss", 0x48000415, 0xb40001ea, "e,f,g", 0 }, +{ "i2st.sd", 0x48000495, 0xb400016a, "e,f,g", 0 }, +{ "i2st.dd", 0x48000595, 0xb400006a, "e,f,g", 0 }, +{ "i2as1.ss", 0x48000416, 0xb40001e9, "e,f,g", 0 }, +{ "i2as1.sd", 0x48000496, 0xb4000169, "e,f,g", 0 }, +{ "i2as1.dd", 0x48000596, 0xb4000069, "e,f,g", 0 }, +{ "i2ast.ss", 0x48000417, 0xb40001e8, "e,f,g", 0 }, +{ "i2ast.sd", 0x48000497, 0xb4000168, "e,f,g", 0 }, +{ "i2ast.dd", 0x48000597, 0xb4000068, "e,f,g", 0 }, +{ "rat1s2.ss", 0x48000418, 0xb40001e7, "e,f,g", 0 }, +{ "rat1s2.sd", 0x48000498, 0xb4000167, "e,f,g", 0 }, +{ "rat1s2.dd", 0x48000598, 0xb4000067, "e,f,g", 0 }, +{ "m12asm.ss", 0x48000419, 0xb40001e6, "e,f,g", 0 }, +{ "m12asm.sd", 0x48000499, 0xb4000166, "e,f,g", 0 }, +{ "m12asm.dd", 0x48000599, 0xb4000066, "e,f,g", 0 }, +{ "ra1s2.ss", 0x4800041a, 0xb40001e5, "e,f,g", 0 }, +{ "ra1s2.sd", 0x4800049a, 0xb4000165, "e,f,g", 0 }, +{ "ra1s2.dd", 0x4800059a, 0xb4000065, "e,f,g", 0 }, +{ "m12ttsa.ss", 0x4800041b, 0xb40001e4, "e,f,g", 0 }, +{ "m12ttsa.sd", 0x4800049b, 0xb4000164, "e,f,g", 0 }, +{ "m12ttsa.dd", 0x4800059b, 0xb4000064, "e,f,g", 0 }, +{ "iat1s2.ss", 0x4800041c, 0xb40001e3, "e,f,g", 0 }, +{ "iat1s2.sd", 0x4800049c, 0xb4000163, "e,f,g", 0 }, +{ "iat1s2.dd", 0x4800059c, 0xb4000063, "e,f,g", 0 }, +{ "m12tsm.ss", 0x4800041d, 0xb40001e2, "e,f,g", 0 }, +{ "m12tsm.sd", 0x4800049d, 0xb4000162, "e,f,g", 0 }, +{ "m12tsm.dd", 0x4800059d, 0xb4000062, "e,f,g", 0 }, +{ "ia1s2.ss", 0x4800041e, 0xb40001e1, "e,f,g", 0 }, +{ "ia1s2.sd", 0x4800049e, 0xb4000161, "e,f,g", 0 }, +{ "ia1s2.dd", 0x4800059e, 0xb4000061, "e,f,g", 0 }, +{ "m12tsa.ss", 0x4800041f, 0xb40001e0, "e,f,g", 0 }, +{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, +{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */ +{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, +{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, +{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, +{ "mr2pt.ss", 0x48000001, 0xb40005fe, "e,f,g", 0 }, +{ "mr2pt.sd", 0x48000081, 0xb400057e, "e,f,g", 0 }, +{ "mr2pt.dd", 0x48000181, 0xb400047e, "e,f,g", 0 }, +{ "mr2mp1.ss", 0x48000002, 0xb40005fd, "e,f,g", 0 }, +{ "mr2mp1.sd", 0x48000082, 0xb400057d, "e,f,g", 0 }, +{ "mr2mp1.dd", 0x48000182, 0xb400047d, "e,f,g", 0 }, +{ "mr2mpt.ss", 0x48000003, 0xb40005fc, "e,f,g", 0 }, +{ "mr2mpt.sd", 0x48000083, 0xb400057c, "e,f,g", 0 }, +{ "mr2mpt.dd", 0x48000183, 0xb400047c, "e,f,g", 0 }, +{ "mi2p1.ss", 0x48000004, 0xb40005fb, "e,f,g", 0 }, +{ "mi2p1.sd", 0x48000084, 0xb400057b, "e,f,g", 0 }, +{ "mi2p1.dd", 0x48000184, 0xb400047b, "e,f,g", 0 }, +{ "mi2pt.ss", 0x48000005, 0xb40005fa, "e,f,g", 0 }, +{ "mi2pt.sd", 0x48000085, 0xb400057a, "e,f,g", 0 }, +{ "mi2pt.dd", 0x48000185, 0xb400047a, "e,f,g", 0 }, +{ "mi2mp1.ss", 0x48000006, 0xb40005f9, "e,f,g", 0 }, +{ "mi2mp1.sd", 0x48000086, 0xb4000579, "e,f,g", 0 }, +{ "mi2mp1.dd", 0x48000186, 0xb4000479, "e,f,g", 0 }, +{ "mi2mpt.ss", 0x48000007, 0xb40005f8, "e,f,g", 0 }, +{ "mi2mpt.sd", 0x48000087, 0xb4000578, "e,f,g", 0 }, +{ "mi2mpt.dd", 0x48000187, 0xb4000478, "e,f,g", 0 }, +{ "mrmt1p2.ss", 0x48000008, 0xb40005f7, "e,f,g", 0 }, +{ "mrmt1p2.sd", 0x48000088, 0xb4000577, "e,f,g", 0 }, +{ "mrmt1p2.dd", 0x48000188, 0xb4000477, "e,f,g", 0 }, +{ "mm12mpm.ss", 0x48000009, 0xb40005f6, "e,f,g", 0 }, +{ "mm12mpm.sd", 0x48000089, 0xb4000576, "e,f,g", 0 }, +{ "mm12mpm.dd", 0x48000189, 0xb4000476, "e,f,g", 0 }, +{ "mrm1p2.ss", 0x4800000a, 0xb40005f5, "e,f,g", 0 }, +{ "mrm1p2.sd", 0x4800008a, 0xb4000575, "e,f,g", 0 }, +{ "mrm1p2.dd", 0x4800018a, 0xb4000475, "e,f,g", 0 }, +{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 }, +{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 }, +{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 }, +{ "mimt1p2.ss", 0x4800000c, 0xb40005f3, "e,f,g", 0 }, +{ "mimt1p2.sd", 0x4800008c, 0xb4000573, "e,f,g", 0 }, +{ "mimt1p2.dd", 0x4800018c, 0xb4000473, "e,f,g", 0 }, +{ "mm12tpm.ss", 0x4800000d, 0xb40005f2, "e,f,g", 0 }, +{ "mm12tpm.sd", 0x4800008d, 0xb4000572, "e,f,g", 0 }, +{ "mm12tpm.dd", 0x4800018d, 0xb4000472, "e,f,g", 0 }, +{ "mim1p2.ss", 0x4800000e, 0xb40005f1, "e,f,g", 0 }, +{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, +{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, + +/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */ +{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, +{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, +{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, +{ "mr2st.ss", 0x48000011, 0xb40005ee, "e,f,g", 0 }, +{ "mr2st.sd", 0x48000091, 0xb400056e, "e,f,g", 0 }, +{ "mr2st.dd", 0x48000191, 0xb400046e, "e,f,g", 0 }, +{ "mr2ms1.ss", 0x48000012, 0xb40005ed, "e,f,g", 0 }, +{ "mr2ms1.sd", 0x48000092, 0xb400056d, "e,f,g", 0 }, +{ "mr2ms1.dd", 0x48000192, 0xb400046d, "e,f,g", 0 }, +{ "mr2mst.ss", 0x48000013, 0xb40005ec, "e,f,g", 0 }, +{ "mr2mst.sd", 0x48000093, 0xb400056c, "e,f,g", 0 }, +{ "mr2mst.dd", 0x48000193, 0xb400046c, "e,f,g", 0 }, +{ "mi2s1.ss", 0x48000014, 0xb40005eb, "e,f,g", 0 }, +{ "mi2s1.sd", 0x48000094, 0xb400056b, "e,f,g", 0 }, +{ "mi2s1.dd", 0x48000194, 0xb400046b, "e,f,g", 0 }, +{ "mi2st.ss", 0x48000015, 0xb40005ea, "e,f,g", 0 }, +{ "mi2st.sd", 0x48000095, 0xb400056a, "e,f,g", 0 }, +{ "mi2st.dd", 0x48000195, 0xb400046a, "e,f,g", 0 }, +{ "mi2ms1.ss", 0x48000016, 0xb40005e9, "e,f,g", 0 }, +{ "mi2ms1.sd", 0x48000096, 0xb4000569, "e,f,g", 0 }, +{ "mi2ms1.dd", 0x48000196, 0xb4000469, "e,f,g", 0 }, +{ "mi2mst.ss", 0x48000017, 0xb40005e8, "e,f,g", 0 }, +{ "mi2mst.sd", 0x48000097, 0xb4000568, "e,f,g", 0 }, +{ "mi2mst.dd", 0x48000197, 0xb4000468, "e,f,g", 0 }, +{ "mrmt1s2.ss", 0x48000018, 0xb40005e7, "e,f,g", 0 }, +{ "mrmt1s2.sd", 0x48000098, 0xb4000567, "e,f,g", 0 }, +{ "mrmt1s2.dd", 0x48000198, 0xb4000467, "e,f,g", 0 }, +{ "mm12msm.ss", 0x48000019, 0xb40005e6, "e,f,g", 0 }, +{ "mm12msm.sd", 0x48000099, 0xb4000566, "e,f,g", 0 }, +{ "mm12msm.dd", 0x48000199, 0xb4000466, "e,f,g", 0 }, +{ "mrm1s2.ss", 0x4800001a, 0xb40005e5, "e,f,g", 0 }, +{ "mrm1s2.sd", 0x4800009a, 0xb4000565, "e,f,g", 0 }, +{ "mrm1s2.dd", 0x4800019a, 0xb4000465, "e,f,g", 0 }, +{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 }, +{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 }, +{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 }, +{ "mimt1s2.ss", 0x4800001c, 0xb40005e3, "e,f,g", 0 }, +{ "mimt1s2.sd", 0x4800009c, 0xb4000563, "e,f,g", 0 }, +{ "mimt1s2.dd", 0x4800019c, 0xb4000463, "e,f,g", 0 }, +{ "mm12tsm.ss", 0x4800001d, 0xb40005e2, "e,f,g", 0 }, +{ "mm12tsm.sd", 0x4800009d, 0xb4000562, "e,f,g", 0 }, +{ "mm12tsm.dd", 0x4800019d, 0xb4000462, "e,f,g", 0 }, +{ "mim1s2.ss", 0x4800001e, 0xb40005e1, "e,f,g", 0 }, +{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, +{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, + +{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.ss", 0x48000420, 0xb40001df, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.sd", 0x480004a0, 0xb400015f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul.dd", 0x480005a0, 0xb400005f, "e,f,g", 0 }, /* pfmul.p fsrc1,fsrc2,fdest */ +{ "pfmul3.dd", 0x480005a4, 0xb400005b, "e,f,g", 0 }, /* pfmul3.p fsrc1,fsrc2,fdest */ +{ "fmlow.dd", 0x480001a1, 0xb400045e, "e,f,g", 0 }, /* fmlow.dd fsrc1,fsrc2,fdest */ +{ "frcp.ss", 0x48000022, 0xb40005dd, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.sd", 0x480000a2, 0xb400055d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frcp.dd", 0x480001a2, 0xb400045d, "f,g", 0 }, /* frcp.p fsrc2,fdest */ +{ "frsqr.ss", 0x48000023, 0xb40005dc, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.sd", 0x480000a3, 0xb400055c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "frsqr.dd", 0x480001a3, 0xb400045c, "f,g", 0 }, /* frsqr.p fsrc2,fdest */ +{ "fadd.ss", 0x48000030, 0xb40005cf, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.sd", 0x480000b0, 0xb400054f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "fadd.dd", 0x480001b0, 0xb400044f, "e,f,g", 0 }, /* fadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.ss", 0x48000430, 0xb40001cf, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.sd", 0x480004b0, 0xb400014f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "pfadd.dd", 0x480005b0, 0xb400004f, "e,f,g", 0 }, /* pfadd.p fsrc1,fsrc2,fdest */ +{ "fsub.ss", 0x48000031, 0xb40005ce, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.sd", 0x480000b1, 0xb400054e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "fsub.dd", 0x480001b1, 0xb400044e, "e,f,g", 0 }, /* fsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.ss", 0x48000431, 0xb40001ce, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.sd", 0x480004b1, 0xb400014e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "pfsub.dd", 0x480005b1, 0xb400004e, "e,f,g", 0 }, /* pfsub.p fsrc1,fsrc2,fdest */ +{ "fix.sd", 0x480000b2, 0xb400054d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "fix.dd", 0x480001b2, 0xb400044d, "e,g", 0 }, /* fix.p fsrc1,fdest */ +{ "pfix.sd", 0x480004b2, 0xb400014d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "pfix.dd", 0x480005b2, 0xb400004d, "e,g", 0 }, /* pfix.p fsrc1,fdest */ +{ "famov.ss", 0x48000033, 0xb40005cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "famov.dd", 0x480001b3, 0xb400044c, "e,g", 0 }, /* famov.p fsrc1,fdest */ +{ "pfamov.ss", 0x48000433, 0xb40001cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ +/* Opcode pfgt has R bit cleared; pfle has R bit set. */ +{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ +{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "pfeq.dd", 0x48000535, 0xb40000ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ +{ "ftrunc.sd", 0x480000ba, 0xb4000545, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "ftrunc.dd", 0x480001ba, 0xb4000445, "e,g", 0 }, /* ftrunc.p fsrc1,fdest */ +{ "pftrunc.sd", 0x480004ba, 0xb4000145, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "pftrunc.dd", 0x480005ba, 0xb4000045, "e,g", 0 }, /* pftrunc.p fsrc1,fdest */ +{ "fxfr", 0x48000040, 0xb40005bf, "e,d", 0 }, /* fxfr fsrc1,idest */ +{ "fiadd.ss", 0x48000049, 0xb40005b6, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "fiadd.dd", 0x480001c9, 0xb4000436, "e,f,g", 0 }, /* fiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.ss", 0x48000449, 0xb40001b6, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "pfiadd.dd", 0x480005c9, 0xb4000036, "e,f,g", 0 }, /* pfiadd.w fsrc1,fsrc2,fdest */ +{ "fisub.ss", 0x4800004d, 0xb40005b2, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "fisub.dd", 0x480001cd, 0xb4000432, "e,f,g", 0 }, /* fisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.ss", 0x4800044d, 0xb40001b2, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "pfisub.dd", 0x480005cd, 0xb4000032, "e,f,g", 0 }, /* pfisub.w fsrc1,fsrc2,fdest */ +{ "fzchkl", 0x480001d7, 0xb4000428, "e,f,g", 0 }, /* fzchkl fsrc1,fsrc2,fdest */ +{ "pfzchkl", 0x480005d7, 0xb4000028, "e,f,g", 0 }, /* pfzchkl fsrc1,fsrc2,fdest */ +{ "fzchks", 0x480001df, 0xb4000420, "e,f,g", 0 }, /* fzchks fsrc1,fsrc2,fdest */ +{ "pfzchks", 0x480005df, 0xb4000020, "e,f,g", 0 }, /* pfzchks fsrc1,fsrc2,fdest */ +{ "faddp", 0x480001d0, 0xb400042f, "e,f,g", 0 }, /* faddp fsrc1,fsrc2,fdest */ +{ "pfaddp", 0x480005d0, 0xb400002f, "e,f,g", 0 }, /* pfaddp fsrc1,fsrc2,fdest */ +{ "faddz", 0x480001d1, 0xb400042e, "e,f,g", 0 }, /* faddz fsrc1,fsrc2,fdest */ +{ "pfaddz", 0x480005d1, 0xb400002e, "e,f,g", 0 }, /* pfaddz fsrc1,fsrc2,fdest */ +{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ +{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ + +/* Floating point pseudo-instructions. */ +{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ +{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ +{ "fmov.sd", 0x480000b3, 0xb400054c, "e,g", 0 }, /* famov.sd fsrc1,fdest */ +{ "fmov.ds", 0x48000133, 0xb40004cc, "e,g", 0 }, /* famov.ds fsrc1,fdest */ +{ "pfmov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.ds fsrc1,fdest */ +{ "pfmov.dd", 0x480005c9, 0xb7e00036, "e,g", 0 }, /* pfiadd.dd fsrc1,f0,fdest */ +{ 0, 0, 0, 0, 0 }, + +}; + +#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0])) + + diff --git a/ld/Makefile.am b/ld/Makefile.am index b6244d08c8b..5a20e9378e6 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -1,6 +1,7 @@ ## Process this file with automake to generate Makefile.in # # Copyright (C) 2012-2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -214,6 +215,7 @@ ALL_EMULATION_SOURCES = \ ed30v_o.c \ ed30velf.c \ eelf32_dlx.c \ + eelf32_i860.c \ eelf32_sparc.c \ eelf32_sparc_sol2.c \ eelf32_sparc_vxworks.c \ diff --git a/ld/Makefile.in b/ld/Makefile.in index 60f0264d046..725cc95326d 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -729,6 +729,7 @@ ALL_EMULATION_SOURCES = \ ed30v_o.c \ ed30velf.c \ eelf32_dlx.c \ + eelf32_i860.c \ eelf32_sparc.c \ eelf32_sparc_sol2.c \ eelf32_sparc_vxworks.c \ @@ -1338,6 +1339,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ed30v_o.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ed30velf.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_dlx.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_i860.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_sparc.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_sparc_sol2.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32_sparc_vxworks.Po@am__quote@ diff --git a/ld/configure.tgt b/ld/configure.tgt index 55eb6e94b84..cb7145f6ce5 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -1,6 +1,7 @@ # configure.tgt # # Copyright (C) 2013-2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -70,7 +71,9 @@ if test "${ac_default_ld_warn_execstack}" = 2; then # The HPPA port needs to support older kernels that # use executable stacks for signals and syscalls. # Many MIPS targets use executable stacks. + # The i860 MMU has no execute permission for an executable stack to add. hppa*-*-* | \ + i860-*-* | \ mips*-*-*) ac_default_ld_warn_execstack=0 ;; @@ -423,6 +426,9 @@ i[3-7]86-*-chaos) targ_emul=elf_i386_chaos ia16-*-elf*) targ_emul=elf_i386 targ_extra_emuls=i386msdos ;; +i860-stardent-sysv4* | i860-stardent-elf* | i860-*-linux*) + targ_emul=elf32_i860 + ;; ia64-*-elf*) targ_emul=elf64_ia64 ;; ia64-*-freebsd* | ia64-*-kfreebsd*-gnu) diff --git a/ld/emulparams/elf32_i860.sh b/ld/emulparams/elf32_i860.sh new file mode 100644 index 00000000000..a3803ac6a3d --- /dev/null +++ b/ld/emulparams/elf32_i860.sh @@ -0,0 +1,24 @@ +# A work in progress... +# Copyright (C) 2026 René Rebe +SCRIPT_NAME=elf +TEMPLATE_NAME=generic +EXTRA_EM_FILE=genelf +OUTPUT_FORMAT="elf32-i860-little" +BIG_OUTPUT_FORMAT="elf32-i860" +LITTLE_OUTPUT_FORMAT="elf32-i860-little" +NO_REL_RELOCS=yes +TEXT_START_ADDR=0 +PAGE_SIZE=0x1000 +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +ARCH=i860 + +case "$target" in + i860-*-linux*) + TEMPLATE_NAME=elf + EXTRA_EM_FILE= + TEXT_START_ADDR=0x10000 + GENERATE_SHLIB_SCRIPT=yes + GENERATE_PIE_SCRIPT=yes + COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" + ;; +esac diff --git a/ld/po/BLD-POTFILES.in b/ld/po/BLD-POTFILES.in index fe46c510261..ebbe0c78ffd 100644 --- a/ld/po/BLD-POTFILES.in +++ b/ld/po/BLD-POTFILES.in @@ -73,6 +73,7 @@ ed30v_e.c ed30v_o.c ed30velf.c eelf32_dlx.c +eelf32_i860.c eelf32_sparc.c eelf32_sparc_sol2.c eelf32_sparc_vxworks.c diff --git a/ld/testsuite/ld-i860/ehframe-hdr.d b/ld/testsuite/ld-i860/ehframe-hdr.d new file mode 100644 index 00000000000..a6bb9537001 --- /dev/null +++ b/ld/testsuite/ld-i860/ehframe-hdr.d @@ -0,0 +1,9 @@ +#source: ehframe.s +#as: +#ld: -shared --eh-frame-hdr +#readelf: -wf +#... +.*FDE.*pc=0*[1-9a-f][0-9a-f]*\.\.[0-9a-f]+ +#... +.*FDE.*pc=0*[1-9a-f][0-9a-f]*\.\.[0-9a-f]+ +#pass diff --git a/ld/testsuite/ld-i860/ehframe.s b/ld/testsuite/ld-i860/ehframe.s new file mode 100644 index 00000000000..b8ede66257c --- /dev/null +++ b/ld/testsuite/ld-i860/ehframe.s @@ -0,0 +1,115 @@ +# gcc -O2 -fPIC -fexceptions: gas has no CFI directives for i860, GCC writes .eh_frame itself + .text + .align 8 + .globl f1 + .type f1, @function + .long .ep.f1-f1+0xc8000000 + nop +f1: +.LFB0: + addu -16,%sp,%sp +.LCFI0: + st.l %fp,0(%sp) +.LCFI1: + addu 0,%sp,%fp +.LCFI2: + st.l %r1,4(%fp) +.LCFI3: +.ep.f1: + call g@plt + nop + addu 1,%r16,%r16 + ld.l 4(%fp),%r1 + ld.l 0(%fp),%fp + bri %r1 + addu 16,%sp,%sp +.LFE0: + .size f1, .-f1 + .align 8 + .globl f2 + .type f2, @function + .long .ep.f2-f2+0xc8000000 + nop +f2: +.LFB1: + addu -16,%sp,%sp +.LCFI4: + st.l %fp,0(%sp) +.LCFI5: + addu 0,%sp,%fp +.LCFI6: + st.l %r1,4(%fp) +.LCFI7: +.ep.f2: + call g@plt + nop + addu 2,%r16,%r16 + ld.l 4(%fp),%r1 + ld.l 0(%fp),%fp + bri %r1 + addu 16,%sp,%sp +.LFE1: + .size f2, .-f2 + .section .eh_frame,"aw",@progbits +.Lframe1: + .4byte .LECIE1-.LSCIE1 +.LSCIE1: + .4byte 0 + .byte 0x3 + .string "" + .uleb128 0x1 + .sleb128 -4 + .uleb128 0x1 + .byte 0xc + .uleb128 0x2 + .uleb128 0 + .align 4 +.LECIE1: +.LSFDE1: + .4byte .LEFDE1-.LASFDE1 +.LASFDE1: + .4byte .LASFDE1-.Lframe1 + .4byte .LFB0 + .4byte .LFE0-.LFB0 + .byte 0x4 + .4byte .LCFI0-.LFB0 + .byte 0xe + .uleb128 0x10 + .byte 0x4 + .4byte .LCFI1-.LCFI0 + .byte 0x83 + .uleb128 0x4 + .byte 0x4 + .4byte .LCFI2-.LCFI1 + .byte 0xd + .uleb128 0x3 + .byte 0x4 + .4byte .LCFI3-.LCFI2 + .byte 0x81 + .uleb128 0x3 + .align 4 +.LEFDE1: +.LSFDE3: + .4byte .LEFDE3-.LASFDE3 +.LASFDE3: + .4byte .LASFDE3-.Lframe1 + .4byte .LFB1 + .4byte .LFE1-.LFB1 + .byte 0x4 + .4byte .LCFI4-.LFB1 + .byte 0xe + .uleb128 0x10 + .byte 0x4 + .4byte .LCFI5-.LCFI4 + .byte 0x83 + .uleb128 0x4 + .byte 0x4 + .4byte .LCFI6-.LCFI5 + .byte 0xd + .uleb128 0x3 + .byte 0x4 + .4byte .LCFI7-.LCFI6 + .byte 0x81 + .uleb128 0x3 + .align 4 +.LEFDE3: diff --git a/ld/testsuite/ld-i860/ld-i860.exp b/ld/testsuite/ld-i860/ld-i860.exp new file mode 100644 index 00000000000..bede80e9c10 --- /dev/null +++ b/ld/testsuite/ld-i860/ld-i860.exp @@ -0,0 +1,32 @@ +# Expect script for ld-i860 tests +# Copyright (C) 2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. + +if { ![istarget i860-*-linux*] } { + return +} + +run_dump_test "shared-relocs" +run_dump_test "shared-plt" +run_dump_test "nonpic-shared" +run_dump_test "static-got" +run_dump_test "tls-shared" +run_dump_test "tls-static" +run_dump_test "ehframe-hdr" diff --git a/ld/testsuite/ld-i860/nonpic-shared.d b/ld/testsuite/ld-i860/nonpic-shared.d new file mode 100644 index 00000000000..afc9a542d53 --- /dev/null +++ b/ld/testsuite/ld-i860/nonpic-shared.d @@ -0,0 +1,4 @@ +#source: nonpic.s +#ld: -shared +#error: .*relocation R_860_HIGH against `a local symbol' can not be used when making a shared object; recompile with -fPIC +#name: i860 non-PIC object in a shared library diff --git a/ld/testsuite/ld-i860/nonpic.s b/ld/testsuite/ld-i860/nonpic.s new file mode 100644 index 00000000000..0bf2dff41b7 --- /dev/null +++ b/ld/testsuite/ld-i860/nonpic.s @@ -0,0 +1,5 @@ + .text +f: orh [x]@h,%r0,%r31 + or [x]@l,%r31,%r31 + .data +x: .long 0 diff --git a/ld/testsuite/ld-i860/shared-plt.d b/ld/testsuite/ld-i860/shared-plt.d new file mode 100644 index 00000000000..cca0f57943b --- /dev/null +++ b/ld/testsuite/ld-i860/shared-plt.d @@ -0,0 +1,19 @@ +#source: shared.s +#ld: -shared +#objdump: -d -j .plt +#name: i860 PLT entry + +.*: +file format .* + + +Disassembly of section \.plt: + +[0-9a-f]+ <\.plt>: + +[0-9a-f]+: 00 00 3c a0 shl %r0,%r1,%r28 + +[0-9a-f]+: 01 00 00 6c call .* + +[0-9a-f]+: 00 00 00 a0 shl %r0,%r0,%r0 + +[0-9a-f]+: .. .. 1f ec orh .*,%r0,%r31 + +[0-9a-f]+: 00 08 ff 83 addu %r1,%r31,%r31 + +[0-9a-f]+: .. .. ff 17 ld\.l .*\(%r31\),%r31 + +[0-9a-f]+: 00 f8 00 40 bri %r31 + +[0-9a-f]+: 00 00 81 a3 shl %r0,%r28,%r1 diff --git a/ld/testsuite/ld-i860/shared-relocs.d b/ld/testsuite/ld-i860/shared-relocs.d new file mode 100644 index 00000000000..a73ecd1a76f --- /dev/null +++ b/ld/testsuite/ld-i860/shared-relocs.d @@ -0,0 +1,14 @@ +#source: shared.s +#ld: -shared +#readelf: -r --wide +#name: i860 shared library dynamic relocations + +Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 3 entries: + *Offset +Info +Type +Sym\. *Value +Symbol's Name \+ Addend +[0-9a-f]+ +[0-9a-f]+ +R_860_RELATIVE +[0-9a-f]+ +[0-9a-f]+ +[0-9a-f]+ +R_860_32 +[0-9a-f]+ +gdata \+ 0 +[0-9a-f]+ +[0-9a-f]+ +R_860_GLOB_DAT +[0-9a-f]+ +gdata \+ 0 + +Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entry: + *Offset +Info +Type +Sym\. *Value +Symbol's Name \+ Addend +[0-9a-f]+ +[0-9a-f]+ +R_860_JUMP_SLOT +[0-9a-f]+ +bar \+ 0 diff --git a/ld/testsuite/ld-i860/shared.s b/ld/testsuite/ld-i860/shared.s new file mode 100644 index 00000000000..14ba2c9684b --- /dev/null +++ b/ld/testsuite/ld-i860/shared.s @@ -0,0 +1,32 @@ + .text + .globl foo + .type foo,@function +foo: + call 1f + nop +1: orh [_GLOBAL_OFFSET_TABLE_]@pc@ha,%r0,%r15 + adds [_GLOBAL_OFFSET_TABLE_+4]@pc@l,%r15,%r15 + addu %r1,%r15,%r15 + orh [gdata]@got@ha,%r0,%r31 + addu %r15,%r31,%r31 + ld.l [gdata]@got@l(%r31),%r16 + orh [ldata]@gotoff@h,%r0,%r31 + or [ldata]@gotoff@l,%r31,%r31 + addu %r15,%r31,%r17 + br bar@plt + nop + .size foo,.-foo + .globl bar + .type bar,@function +bar: + bri %r1 + nop + .size bar,.-bar + .data + .globl gdata + .type gdata,@object + .size gdata,4 +gdata: .long 40 +ldata: .long 1 +ptr: .long gdata + .long ldata diff --git a/ld/testsuite/ld-i860/static-got.d b/ld/testsuite/ld-i860/static-got.d new file mode 100644 index 00000000000..aaf532343d0 --- /dev/null +++ b/ld/testsuite/ld-i860/static-got.d @@ -0,0 +1,6 @@ +#source: static-got.s +#ld: -static +#readelf: -r --wide +#name: i860 static link resolves the GOT and PLT + +There are no relocations in this file\. diff --git a/ld/testsuite/ld-i860/static-got.s b/ld/testsuite/ld-i860/static-got.s new file mode 100644 index 00000000000..10864dc9f10 --- /dev/null +++ b/ld/testsuite/ld-i860/static-got.s @@ -0,0 +1,14 @@ + .text + .globl _start +_start: call g@plt + nop + orh [gv]@got@ha,%r0,%r31 + addu %r15,%r31,%r31 + ld.l [gv]@got@l(%r31),%r16 + .globl g + .type g,@function +g: bri %r1 + nop + .data + .globl gv +gv: .long 7 diff --git a/ld/testsuite/ld-i860/tls-shared.d b/ld/testsuite/ld-i860/tls-shared.d new file mode 100644 index 00000000000..56820232995 --- /dev/null +++ b/ld/testsuite/ld-i860/tls-shared.d @@ -0,0 +1,12 @@ +#source: tls.s +#ld: -shared +#readelf: -r --wide +#name: i860 TLS relocations in a shared library + +Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 5 entries: + *Offset +Info +Type +Sym\. *Value +Symbol's Name \+ Addend +[0-9a-f]+ +[0-9a-f]+ +R_860_TLS_DTPMOD32 +0 +[0-9a-f]+ +[0-9a-f]+ +R_860_TLS_TPOFF32 +8 +[0-9a-f]+ +[0-9a-f]+ +R_860_TLS_DTPMOD32 +[0-9a-f]+ +gtd \+ 0 +[0-9a-f]+ +[0-9a-f]+ +R_860_TLS_DTPOFF32 +[0-9a-f]+ +gtd \+ 0 +[0-9a-f]+ +[0-9a-f]+ +R_860_TLS_TPOFF32 +[0-9a-f]+ +gtd \+ 0 diff --git a/ld/testsuite/ld-i860/tls-static.d b/ld/testsuite/ld-i860/tls-static.d new file mode 100644 index 00000000000..874aae67afc --- /dev/null +++ b/ld/testsuite/ld-i860/tls-static.d @@ -0,0 +1,11 @@ +#source: tls.s +#ld: -static -e f +#objdump: -s -j .got +#name: i860 TLS GOT entries in a static link + +.*: +file format .* + +Contents of section \.got: + [0-9a-f]+ 00000000 00000000 00000000 01000000 .* + [0-9a-f]+ 04000000 fcffffff 01000000 00000000 .* + [0-9a-f]+ f4ffffff +.* diff --git a/ld/testsuite/ld-i860/tls.s b/ld/testsuite/ld-i860/tls.s new file mode 100644 index 00000000000..717c9a50fa4 --- /dev/null +++ b/ld/testsuite/ld-i860/tls.s @@ -0,0 +1,20 @@ + .section .tdata,"awT",@progbits + .globl gtd + .type gtd,@object +gtd: .long 0x1234 +ltd: .long 0x5678 + .section .tbss,"awT",@nobits +ltb: .long 0 + .text + .globl f +f: + orh [gtd]@tlsgd@h,%r0,%r31 + or [gtd]@tlsgd@l,%r31,%r31 + orh [ltd]@tlsgd@h,%r0,%r31 + or [ltd]@tlsgd@l,%r31,%r31 + orh [gtd]@gottpoff@ha,%r0,%r31 + addu %r15,%r31,%r31 + ld.l [gtd]@gottpoff@l(%r31),%r16 + orh [ltb]@gottpoff@ha,%r0,%r31 + addu %r15,%r31,%r31 + ld.l [ltb]@gottpoff@l(%r31),%r16 diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index a0fcf4d5ec7..3ebdb6266ba 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -1,6 +1,7 @@ ## Process this file with automake to generate Makefile.in # # Copyright (C) 2012-2026 Free Software Foundation, Inc. +# Copyright (C) 2026 René Rebe # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -156,6 +157,7 @@ TARGET32_LIBOPCODES_CFILES = \ h8300-dis.c \ hppa-dis.c \ i386-dis.c \ + i860-dis.c \ ip2k-asm.c \ ip2k-desc.c \ ip2k-dis.c \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index c5449bebf54..7b5c6c22bfd 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -562,6 +562,7 @@ TARGET32_LIBOPCODES_CFILES = \ h8300-dis.c \ hppa-dis.c \ i386-dis.c \ + i860-dis.c \ ip2k-asm.c \ ip2k-desc.c \ ip2k-dis.c \ @@ -933,6 +934,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/h8300-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/hppa-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i386-dis.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/i860-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ia64-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ia64-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ip2k-asm.Plo@am__quote@ diff --git a/opcodes/configure b/opcodes/configure index 2ae65d00cbd..bc78c7511fe 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -14387,6 +14387,7 @@ if test x${all_targets} = xfalse ; then bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; bfd_i386_arch|bfd_iamcu_arch) ta="$ta i386-dis.lo" ;; + bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index c6d8972aa0a..7bdffbaf033 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -1,6 +1,7 @@ dnl Process this file with autoconf to produce a configure script. dnl dnl Copyright (C) 2012-2026 Free Software Foundation, Inc. +dnl Copyright (C) 2026 René Rebe dnl dnl This file is free software; you can redistribute it and/or modify dnl it under the terms of the GNU General Public License as published by @@ -284,6 +285,7 @@ if test x${all_targets} = xfalse ; then bfd_hppa_arch) ta="$ta hppa-dis.lo" ;; bfd_i386_arch|bfd_iamcu_arch) ta="$ta i386-dis.lo" ;; + bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; bfd_epiphany_arch) ta="$ta epiphany-asm.lo epiphany-desc.lo epiphany-dis.lo epiphany-ibld.lo epiphany-opc.lo" using_cgen=yes ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 77d44bb08db..da971e29ee4 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -1,5 +1,6 @@ /* Select disassembly routine for specified architecture. Copyright (C) 1994-2026 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe This file is part of the GNU opcodes library. @@ -55,6 +56,7 @@ #define ARCH_h8300 #define ARCH_hppa #define ARCH_i386 +#define ARCH_i860 #define ARCH_ip2k #define ARCH_iq2000 #define ARCH_kvx @@ -214,6 +216,11 @@ disassembler (enum bfd_architecture a, disassemble = print_insn_i386; break; #endif +#ifdef ARCH_i860 + case bfd_arch_i860: + disassemble = print_insn_i860; + break; +#endif #ifdef ARCH_ia64 case bfd_arch_ia64: disassemble = print_insn_ia64; diff --git a/opcodes/disassemble.h b/opcodes/disassemble.h index 2157790c947..1be675289d4 100644 --- a/opcodes/disassemble.h +++ b/opcodes/disassemble.h @@ -1,6 +1,7 @@ /* Header only used inside opcodes library for disassemble. Copyright (C) 2017-2026 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -47,6 +48,7 @@ extern int print_insn_hppa (bfd_vma, disassemble_info *); extern int print_insn_i386 (bfd_vma, disassemble_info *); extern int print_insn_i386_att (bfd_vma, disassemble_info *); extern int print_insn_i386_intel (bfd_vma, disassemble_info *); +extern int print_insn_i860 (bfd_vma, disassemble_info *); extern int print_insn_ia64 (bfd_vma, disassemble_info *); extern int print_insn_ip2k (bfd_vma, disassemble_info *); extern int print_insn_iq2000 (bfd_vma, disassemble_info *); diff --git a/opcodes/i860-dis.c b/opcodes/i860-dis.c new file mode 100644 index 00000000000..ab1136e9c89 --- /dev/null +++ b/opcodes/i860-dis.c @@ -0,0 +1,287 @@ +/* Disassembler for the i860. + Copyright (C) 2000-2018 Free Software Foundation, Inc. + Copyright (C) 2026 René Rebe + + Contributed by Jason Eckhardt . + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "disassemble.h" +#include "opcode/i860.h" + +/* Later we should probably choose the prefix based on which OS flavor. */ +#define I860_REG_PREFIX "%" + +/* Integer register names (encoded as 0..31 in the instruction). */ +static const char *const grnames[] = + {"r0", "r1", "sp", "fp", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; + +/* FP register names (encoded as 0..31 in the instruction). */ +static const char *const frnames[] = + {"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"}; + +/* Control/status register names (encoded as 0..11 in the instruction). + Registers bear, ccr, p0, p1, p2 and p3 are XP only. */ +static const char *const crnames[] = + {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr", + "p0", "p1", "p2", "p3", "--", "--", "--", "--" }; + + + +/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */ +#define BITWISE_OP(op) ((op) == 0x30 || (op) == 0x31 \ + || (op) == 0x34 || (op) == 0x35 \ + || (op) == 0x38 || (op) == 0x39 \ + || (op) == 0x3c || (op) == 0x3d \ + || (op) == 0x33 || (op) == 0x37 \ + || (op) == 0x3b || (op) == 0x3f) + + +/* Sign extend N-bit number. */ +static int +sign_ext (unsigned int x, int n) +{ + int t; + t = x >> (n - 1); + t = ((-t) << n) | x; + return t; +} + + +/* Print a PC-relative branch offset. VAL is the sign extended value + from the branch instruction. */ +static void +print_br_address (disassemble_info *info, bfd_vma memaddr, long val) +{ + + long adj = (long)memaddr + 4 + (val << 2); + + (*info->fprintf_func) (info->stream, "0x%08lx", adj); + + /* Attempt to obtain a symbol for the target address. */ + + if (info->print_address_func && adj != 0) + { + (*info->fprintf_func) (info->stream, "\t// "); + (*info->print_address_func) (adj, info); + } +} + + +/* Print one instruction. */ +int +print_insn_i860 (bfd_vma memaddr, disassemble_info *info) +{ + bfd_byte buff[4]; + unsigned int insn, i; + int status; + const struct i860_opcode *opcode = 0; + + status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + /* Note that i860 instructions are always accessed as little endian + data, regardless of the endian mode of the i860. */ + insn = bfd_getl32 (buff); + + status = 0; + i = 0; + while (i860_opcodes[i].name != NULL) + { + opcode = &i860_opcodes[i]; + if ((insn & opcode->match) == opcode->match + && (insn & opcode->lose) == 0) + { + status = 1; + break; + } + ++i; + } + + if (status == 0) + { + /* Instruction not in opcode table. */ + (*info->fprintf_func) (info->stream, ".long %#08x", insn); + } + else + { + const char *s; + int val; + + /* If this a flop (or a shrd) and its dual bit is set, + prefix with 'd.'. */ + if (((insn & 0xfc000000) == 0x48000000 + || (insn & 0xfc000000) == 0xb0000000) + && (insn & 0x200)) + (*info->fprintf_func) (info->stream, "d.%s\t", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s\t", opcode->name); + + for (s = opcode->args; *s; s++) + { + switch (*s) + { + /* Integer register (src1). */ + case '1': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 11) & 0x1f]); + break; + + /* Integer register (src2). */ + case '2': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 21) & 0x1f]); + break; + + /* Integer destination register. */ + case 'd': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + grnames[(insn >> 16) & 0x1f]); + break; + + /* Floating-point register (src1). */ + case 'e': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 11) & 0x1f]); + break; + + /* Floating-point register (src2). */ + case 'f': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 21) & 0x1f]); + break; + + /* Floating-point destination register. */ + case 'g': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + frnames[(insn >> 16) & 0x1f]); + break; + + /* Control register. */ + case 'c': + (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX, + crnames[(insn >> 21) & 0xf]); + break; + + /* 16-bit immediate (sign extend, except for bitwise ops). */ + case 'i': + if (BITWISE_OP ((insn & 0xfc000000) >> 26)) + (*info->fprintf_func) (info->stream, "0x%04x", + (unsigned int) (insn & 0xffff)); + else + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^0, ld.b). */ + case 'I': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xffff), 16)); + break; + + /* 16-bit immediate, aligned (2^1, ld.s). */ + case 'J': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffe), 16)); + break; + + /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l). */ + case 'K': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfffc), 16)); + break; + + /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d). */ + case 'L': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff8), 16)); + break; + + /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q). */ + case 'M': + (*info->fprintf_func) (info->stream, "%d", + sign_ext ((insn & 0xfff0), 16)); + break; + + /* 5-bit immediate (zero extend). */ + case '5': + (*info->fprintf_func) (info->stream, "%d", + ((insn >> 11) & 0x1f)); + break; + + /* Split 16 bit immediate (20..16:10..0). */ + case 's': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^0, st.b). */ + case 'S': + val = ((insn >> 5) & 0xf800) | (insn & 0x07ff); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^1, st.s). */ + case 'T': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fe); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* Split 16 bit immediate, aligned. (2^2, st.l). */ + case 'U': + val = ((insn >> 5) & 0xf800) | (insn & 0x07fc); + (*info->fprintf_func) (info->stream, "%d", + sign_ext (val, 16)); + break; + + /* 26-bit PC relative immediate (lbroff). */ + case 'l': + val = sign_ext ((insn & 0x03ffffff), 26); + print_br_address (info, memaddr, val); + break; + + /* 16-bit PC relative immediate (sbroff). */ + case 'r': + val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16); + print_br_address (info, memaddr, val); + break; + + default: + (*info->fprintf_func) (info->stream, "%c", *s); + break; + } + } + } + + return sizeof (insn); +} + diff --git a/opcodes/po/POTFILES.in b/opcodes/po/POTFILES.in index c8f83622734..1c4af94e8a5 100644 --- a/opcodes/po/POTFILES.in +++ b/opcodes/po/POTFILES.in @@ -67,6 +67,7 @@ h8300-dis.c hppa-dis.c i386-dis.c i386-opc.h +i860-dis.c ia64-asmtab.h ia64-dis.c ia64-opc.c