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include/emmintrin.h:1526:1: error: inlining failed in call to 'always_inline' '_mm_clflush(void const*)': target specific option mismatch
 1526 | _mm_clflush (void const *__A)

--- stressapptest-1.0.11/src/os.h.vanilla	2024-02-09 16:49:02.605879492 +0100
+++ stressapptest-1.0.11/src/os.h	2024-02-09 16:55:04.521908407 +0100
@@ -150,7 +150,7 @@
   inline static void FastFlush(void *vaddr) {
 #ifdef STRESSAPPTEST_CPU_PPC
     asm volatile("dcbf 0,%0; sync" : : "r" (vaddr));
-#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
+#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
     // Put mfence before and after clflush to make sure:
     // 1. The write before the clflush is committed to memory bus;
     // 2. The read after the clflush is hitting the memory bus.
@@ -192,7 +192,7 @@
       asm volatile("dcbf 0,%0" : : "r" (*vaddrs++));
     }
     asm volatile("sync");
-#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
+#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
     // Put mfence before and after clflush to make sure:
     // 1. The write before the clflush is committed to memory bus;
     // 2. The read after the clflush is hitting the memory bus.
@@ -226,7 +226,7 @@
   inline static void FastFlushHint(void *vaddr) {
 #ifdef STRESSAPPTEST_CPU_PPC
     asm volatile("dcbf 0,%0" : : "r" (vaddr));
-#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
+#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
     // From Intel manual:
     // CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed
     // to be ordered by any other fencing, serializing or other CLFLUSH
@@ -248,7 +248,7 @@
   inline static void FastFlushSync() {
 #ifdef STRESSAPPTEST_CPU_PPC
     asm volatile("sync");
-#elif defined(STRESSAPPTEST_CPU_X86_64) || defined(STRESSAPPTEST_CPU_I686)
+#elif defined(STRESSAPPTEST_CPU_X86_64) || (defined(STRESSAPPTEST_CPU_I686) && defined(__SSE2__))
     // Put mfence before and after clflush to make sure:
     // 1. The write before the clflush is committed to memory bus;
     // 2. The read after the clflush is hitting the memory bus.